VDP3104B 查看數據表（PDF） - Micronas

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VDP3104B

Video Processor Family

Micronas 

VDP 31xxB

PRELIMINARY DATA SHEET

2.7. Video Sync Processing

Fig. 2–11 shows a block diagram of the front-end sync

processing. To extract the sync information from the

video signal, a linear phase lowpass filter eliminates all

noise and video contents above 1 MHz. The sync is sep-

arated by a slicer; the sync phase is measured. A vari-

able window can be selected to improve the noise immu-

nity of the slicer. The phase comparator measures the

falling edge of sync, as well as the integrated sync pulse.

The sync phase error is filtered by a phase-locked loop

that is computed by the FP. All timing in the front-end is

derived from a counter that is part of this PLL, and it thus

counts synchronously to the video signal.

A separate hardware block measures the signal back

porch and also allows gathering the maximum/minimum

of the video signal. This information is processed by the

FP and used for gain control and clamping.

For vertical sync separation, the sliced video signal is in-

tegrated. The FP uses the integrator value to derive ver-

tical sync and field information.

The information extracted by the video sync processing

is multiplexed onto the hardware front sync signal (FSY)

and is distributed to the rest of the video processing sys-

tem. The format of the front sync signal is given in

Fig. 2–12.

The data for the vertical deflection, the sawtooth, and the

East-West correction signal is calculated by the

VDP 31xxB. The data is buffered in a FIFO and trans-

ferred to the back-end by a single wire interface.

Frequency and phase characteristics of the analog vid-

eo signal are derived from PLL1. The results are fed to

the scaler unit for data interpolation and orthogonaliza-

tion and to the clock synthesizer for line-locked clock

generation. Horizontal and vertical syncs are latched

with the line-locked clock.

video

input

lowpass

1 MHz

&

syncslicer

horizontal

sync

separation

phase

comparator

&

counter

lowpass

PLL1

front

sync

generator

clamp &

signal

meas.

front-end

timing

clock

synthesizer

syncs

clamping, colorkey, FIFO_write

vertical

sync

separation

Sawtooth

Parabola

Calculation

FIFO

vertical

serial

data

Fig. 2–11: Sync separation block diagram

front sync

skew

vblank

field

clock

H/V syncs

vertical

E/W

sawtooth

input

analog

video

FSY

F0 F1

(not in scale)

Fig. 2–12: Front sync format

14

F1

skew

LSB

F0 reserved

skew not

MSB used

F

V

V: vertical sync

0 = off

Parity

1 = on

F: field #

0 = field 1

1 = field 2

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