3236-00 查看數據表（PDF） - Peregrine Semiconductor
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3236-00 Datasheet PDF : 16 Pages
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PE3236
Product Specification
Pin No. Pin Name Interface Mode
Type
Description
30
fp
ALL
Output
Monitor pin for main divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding VDD pin 31.
31
VDD-fp
ALL
(Note 2) VDD for fp.
32
Dout
Serial, Parallel
Output
Data Out. The MSEL signal and the raw prescaler output are available on Dout through
enhancement register programming.
33
VDD
ALL
34
Cext
ALL
(Note 1)
Output
Same as pin 1.
Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kohm series
resistor. Connecting Cext to an external capacitor will low pass filter the input to the
inverting amplifier used for driving LD.
35
VDD
ALL
36
PD_D
ALL
37
PD_U
ALL
38
VDD-fc
ALL
39
fc
ALL
40
GND
ALL
(Note 1)
Output
(Note 2)
Output
Same as pin 1.
PD_D is pulse down when fp leads fc.
PD_U is pulse down when fc leads fp.
VDD for fc.
Monitor pin for reference divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding VDD pin 38.
Ground.
41
GND
ALL
Ground.
42
fr
43
LD
44
Enh
ALL
ALL
Serial, Parallel
Input
Output,
OD
Input
Reference frequency input.
Lock detect and open drain logical inversion of Cext. When the loop is in lock, LD is
high impedance, otherwise LD is a logic low (“0”).
Enhancement mode. When asserted low (“0”), enhancement register bits are functional.
Note 1:
Note 2:
VDD pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level.
VDD pins 31 and 38 are used to power the fp and fc outputs and can alternatively be left floating or connected to GND to disable the fp and fc
outputs.
Copyright Peregrine Semiconductor Corp. 2003
Page 4 of 16
File No. 70/0026~02E | UTSi CMOS RFIC SOLUTIONS
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