AK4480 查看數據表（PDF） - Asahi Kasei Microdevices
零件编号
产品描述 (功能)
比赛名单
AK4480 Datasheet PDF : 44 Pages
| |||
[AK4480]
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD=VDDL/R=DVDD=5.0V; VSS1-4 =0V; VREFHL/R=AVDD, VREFLL/R= VSS;
Input data = 24bit; RL ≥ 1kΩ; BICK=64fs; Signal Frequency = 1kHz; Sampling Frequency = 44.1kHz;
Measurement bandwidth = 20Hz ~ 20kHz; External Circuit: Figure 20; unless otherwise specified.)
Parameter
min
typ
max
Unit
Resolution
-
-
32
Bits
Dynamic Characteristics (Note 5)
THD+N
fs=44.1kHz
BW=20kHz
0dBFS
−60dBFS
-
-100
-93
dB
-
-51
-
dB
fs=96kHz
0dBFS
-
97
-
dB
BW=40kHz −60dBFS
-
-48
-
dB
fs=192kHz
BW=40kHz
0dBFS
−60dBFS
97
-
dB
-48
-
dB
BW=80kHz −60dBFS
-45
-
dB
Dynamic Range (−60dBFS with A-weighted)
(Note 6)
108
114
dB
S/N (A-weighted)
(Note 7)
108
114
dB
Interchannel Isolation (1kHz)
100
110
dB
DC Accuracy
Interchannel Gain Mismatch
Gain Drift
Output Voltage
Load Capacitance
Load Resistance
-
0
0.3
dB
(Note 8)
-
20
-
ppm/°C
(Note 9)
±2.25
±2.4
±2.55
Vpp
-
-
25
pF
(Note 10)
2
-
-
kΩ
Power Supplies
Power Supply Current
Normal operation (PDN pin = “H”)
AVDD + VDDL/R
-
DVDD (fs ≤ 96kHz)
-
DVDD (fs = 192kHz)
-
Power down (PDN pin = “L”)
(Note 11)
AVDD+VDDL/R+DVDD
-
30
45
mA
15
-
mA
24
36
mA
10
100
μA
Note 5. Measured by Audio Precision, System Two. Averaging mode. Refer to the evaluation board manual.
Note 6. Figure 20 External LPF Circuit Example 2. 100dB for 16-bit data.
Note 7. Figure 20 External LPF Circuit Example 2. S/N does not depend on input data size.
Note 8. The voltage on (VREFH − VREFL) is held +5V externally.
Note 9. Full-scale voltage(0dB). Output voltage scales with the voltage of (VREFHL/R − VREFLL/R).
AOUT (typ.@0dB) = (AOUT+) − (AOUT−) = ±2.4Vpp × (VREFHL/R − VREFLL/R)/5.
Note 10. Regarding Load Resistance, AC load is 2kΩ (min) with a DC cut capacitor. Please refer to Figure 20. The load
resistance is 4k ohm (min) to ground when without a DC cut capacitor. Please refer to Figure 19. Load Resistance
is with respect to ground. Analog characteristics are sensitive to capacitive load that is connected output pin.
Therefore the capacitive load must be minimized.
Note 11. In the power down mode. P/S pin = DVDD, and all other digital input pins including clock pins
(MCLK, BICK and LRCK) are held VSS4.
MS1146-E-03
-7-
2012/01
Share Link: 