Philips Semiconductors
Multiple voltage regulator with
switch and ignition buffer
Product specification
TDA3681A
SYMBOL
PARAMETER
CONDITIONS
Reset and hold buffer
Isink(L)
ILO
Isource(H)
LOW-level sink current
output leakage current
HIGH-level source
current
tr
rise time
tf
fall time
Reset delay
VRES ≤ 0.8 V; VHOLD ≤ 0.8 V
VHOLD = 5 V
VRES = 5 V
note 4
note 4
Ich
Idch
Vth(r)(RES)
Vth(f)(RES)
td(RES)
td(SW)
reset delay capacitor
charge current
reset delay capacitor
discharge current
rising voltage threshold
reset signal
falling voltage threshold
reset signal
delay reset signal
delay power switch
foldback protection
VCRES = 0 V
VCRES = 3 V;
VP1 = VP2 = 4.3 V
CCRES = 47 nF; note 5
CCRES = 47 nF; note 6
Regulator 1 (IREG1 = 5 mA; unless otherwise specified)
Vo(off)
Vo(REG1)
∆Vline
∆Vload
Iq
SVRR
output voltage off
output voltage
line regulation
load regulation
quiescent current
supply voltage ripple
rejection
1 mA ≤ IREG1 ≤ 600 mA
9.5 V ≤ VP1 ≤ 18 V
9.5 V ≤ VP1 ≤ 18 V
1 mA ≤ IREG1 ≤ 600 mA
IREG1 = 600 mA
fi = 3 kHz; Vi = 2 V (p-p)
Vdrop(REG1) drop-out voltage
Im(REG1)
Isc(REG1)
current limit
short-circuit current
IREG1 = 550 mA;
VP1 = 8.55 V; note 7
VREG1 > 7 V; note 8
RL ≤ 0.5 Ω; note 9
Regulator 2 (IREG2 = 5 mA; unless otherwise specified)
Vo(REG2)
output voltage
∆Vline
∆Vload
line regulation
load regulation
0.5 mA ≤ IREG2 ≤ 300 mA
7 V ≤ VP1 ≤ 18 V
18 V ≤ VP1 ≤ 50 V;
IREG2 ≤ 150 mA
6 V ≤ VP1 ≤ 18 V
6 V ≤ VP1 ≤ 50 V
1 mA ≤ IREG2 ≤ 150 mA
1 mA ≤ IREG2 ≤ 300 mA
MIN.
TYP.
2
−
−
0.1
240 400
−
7
−
1
2
4
1.0 1.6
2.5 3.0
1.0 1.2
20 35
8
17.6
−
1
8.0 8.5
8.0 8.5
−
2
−
20
−
25
60 70
−
0.4
0.65 1.2
250 800
4.75 5.0
4.75 5.0
4.75 5.0
−
2
−
15
−
20
−
−
MAX.
UNIT
−
mA
5
µA
900
µA
50
µs
50
µs
8
µA
−
mA
3.5
V
1.4
V
70
ms
40
ms
400
mV
9.0
V
9.0
V
75
mV
85
mV
60
mA
−
dB
0.7
V
−
A
−
mA
5.25
V
5.25
V
5.25
V
50
mV
75
mV
50
mV
100
mV
2003 Aug 29
11