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LT3060EDC 查看數據表(PDF) - Linear Technology

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LT3060EDC Datasheet PDF : 26 Pages
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LT3060 Series
Applications Information
Table 1 shows 1% resistor divider values for some com-
mon output voltages with a resistor divider current of
about 5µA.
Table 1. Output Voltage Resistor Divider Values
VOUT
R1
R2
(V)
(k Ω)
(k Ω)
1.2
118
118
1.5
121
182
1.8
124
249
2.5
115
365
3
124
499
3.3
124
562
5
115
845
Bypass Capacitance, Output Voltage Noise and
Transient Response
The LT3060 regulators provide low output voltage noise
over the 10Hz to 100kHz bandwidth while operating at
full load with the addition of a reference bypass capacitor
(CREF/BYP) from the REF/BYP pin to GND. A good quality,
low leakage capacitor is recommended. This capacitor
bypasses the internal reference of the regulator, provid-
ing a low frequency noise pole. With the use of 10nF for
CREF/BYP, the output voltage noise decreases to as low as
30µVRMS when the output voltage is set for 0.6V. For higher
output voltages (generated by using a feedback resistor
divider), the output voltage noise gains up accordingly
when using CREF/BYP by itself.
To lower the output voltage noise for higher output volt-
ages, include a feedforward capacitor (CFF) from VOUT
to the ADJ pin. A good quality, low leakage capacitor is
recommended. This capacitor bypasses the error amplifier
of the regulator, providing a low frequency noise pole. With
the use of 10nF for both CFF and CREF/BYP, output voltage
noise decreases to 30µVRMS when the output voltage is
set to 5V by a 5µA feedback resistor divider. If the current
in the feedback resistor divider is doubled, CFF must also
be doubled to achieve equivalent noise performance.
Higher values of output voltage noise are often measured
if care is not exercised with regard to circuit layout and
testing. Crosstalk from nearby traces induces unwanted
noise onto the LT3060’s output. Power supply ripple rejec-
tion must also be considered. The LT3060 regulators do
not have unlimited power supply rejection and will pass a
small portion of the input noise through to the output.
Using a feedforward capacitor (CFF) from VOUT to the ADJ
pin has the added benefit of improving transient response
for output voltages greater than 0.6V. With no feedforward
capacitor, the settling time will increase as the output
voltage is raised above 0.6V. Use the equation in Figure 2
to determine the minimum value of CFF to achieve a
transient response that is similar to 0.6V output voltage
performance regardless of the chosen output voltage
(see Figure 3 and Transient Response in the Typical Perf­
ormance Characteristics section).
IN
OUT
VIN
LT3060
R2
SHDN ADJ
GND REF/BYP R1
CREF/BYP
3060 F02
VOUT
CFF
COUT
( ) CFF
4.7nF
5µA
IFBDIVIDER
IFBDIVIDER
=
VOUT
R1+ R2
0
100pF
1nF
10nF
LOAD CURRENT
100mA/DIV
VOUT = 5V
COUT = 10µF
IFB-DIVIDER = 5µA
100µs/DIV
3060 F03
Figure 2. Feedforward Capacitor for Fast Transient Response
Figure 3. Transient Response vs Feedforward Capacitor
3060fa
17

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