M95320-MB3 查看數據表（PDF） - STMicroelectronics

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M95320-MB3

32Kbit and 64Kbit Serial SPI Bus EEPROMs With High Speed Clock

STMicroelectronics 

M95640, M95320

Read Status Register (RDSR)

The Read Status Register (RDSR) instruction al-

lows the Status Register to be read. The Status

Register may be read at any time, even while a

Write or Write Status Register cycle is in progress.

When one of these cycles is in progress, it is rec-

ommended to check the Write In Progress (WIP)

bit before sending a new instruction to the device.

It is also possible to read the Status Register con-

tinuously, as shown in Figure 10..

The status and control bits of the Status Register

are as follows:

WIP bit. The Write In Progress (WIP) bit indicates

whether the memory is busy with a Write or Write

Status Register cycle. When set to 1, such a cycle

is in progress, when reset to 0 no such cycle is in

progress.

WEL bit. The Write Enable Latch (WEL) bit indi-

cates the status of the internal Write Enable Latch.

When set to 1 the internal Write Enable Latch is

set, when set to 0 the internal Write Enable Latch

is reset and no Write or Write Status Register in-

struction is accepted.

BP1, BP0 bits. The Block Protect (BP1, BP0) bits

are non-volatile. They define the size of the area to

be software protected against Write instructions.

These bits are written with the Write Status Regis-

ter (WRSR) instruction. When one or both of the

Block Protect (BP1, BP0) bits is set to 1, the rele-

vant memory area (as defined in Table 4.) be-

comes protected against Write (WRITE)

instructions. The Block Protect (BP1, BP0) bits

can be written provided that the Hardware Protect-

ed mode has not been set.

SRWD bit. The Status Register Write Disable

(SRWD) bit is operated in conjunction with the

Write Protect (W) signal. The Status Register

Write Disable (SRWD) bit and Write Protect (W)

signal allow the device to be put in the Hardware

Protected mode (when the Status Register Write

Disable (SRWD) bit is set to 1, and Write Protect

(W) is driven Low). In this mode, the non-volatile

bits of the Status Register (SRWD, BP1, BP0) be-

come read-only bits and the Write Status Register

(WRSR) instruction is no longer accepted for exe-

cution.

Figure 10. Read Status Register (RDSR) Sequence

S

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

C

Instruction

D

Status Register Out

Status Register Out

High Impedance

Q

76543210765432107

MSB

MSB

AI02031E

15/42

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