PI6C2308 查看數據表（PDF） - Pericom Semiconductor

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PI6C2308

3.3V Zero-Delay Buffer

Pericom Semiconductor 

PI6C2308

3.3V Zero Delay Buffer 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122

Switching Characteristics(5) for Commercial Temperature Device

Parame te rs

Name

Test Conditions

Min. Typ. Max. Units

t1

Output Frequency

15pF to 30pF load

10

134 MHz

Duty Cycle(5) = t2 ÷ t1 (2308-1H)

Measured at 1.4V, for high drive output

45 50 55

t2

Duty Cycle = t2 ÷ t1

(2308-1, -2, -3, -4, -6)

%

Measured at 1.4V, for normal drive output 40 50 60

Rise Time(4) @30pF

2.2

t3

Rise Time(4) @15pF

Rise Time(4) @30pF (–1H)

Fall Time(4) @30pF

Measured between 0.8V and 2.0V

1.5

1.5

ns

2.2

t4

Fall Time(4) @15pF

1.5

Fall Time(4) @30pF (–1H)

1.25

Output to Output Skew(4) on same

bank (2308–1,–1H,–2,–3,–4,–6)

All outputs equally loaded, VDD/2

200

t5

Output Bank A to Output Bank B

Skew(4) (2308–1,–1H,–4)

All outputs equally loaded, VDD/2

200

t6

(Phase

Error)

Output Bank A to Output Bank B

Skew(4) (2308–2,–3,–6)

All outputs equally loaded, VDD/2

Input to Output Delay, REF Rising Edge

to FBK Rising Edge(4)

Measured at VDD/2

400

ps

0 ±200

t7

Device to Device Skew(4)

Measured at VDD/2 on the

FBK pins of devices

0 600

t8

Output Slew Rate(4)

tJ

Cycle-to-Cycle Jitter(4)

(2308–1,–1H,–4)

tJ

Cycle-to-Cycle Jitter(4)

(2308–2,–3,–6)

Measured between 0.8V and 2.0V on -

1H device using

1

Test Circuit #2

Measured at 66.67 MHz,

loaded 30pF outputs

Measured at 133 MHz,

loaded 15pF outputs

Measured at 66.6 MHz,

loaded 30pF outputs

V/ns

200

100 ps

400

tLOCK

PLL Lock Time(4)

Stable power supply, valid clocks

presented on REF and FBK pins

1.0 ms

Notes:

1. Weak pull-down.

2. Weak pull-down on all outputs.

3. Weak pull-ups on these inputs.

4. REF and FBK inputs have a threshhold voltage of VDD/2.

5. For definition of t1-8, see Switching Waveforms on page 8.

5

PS8384D 06/26/01

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