V53C8125H30 查看數據表（PDF） - Mosel Vitelic Corporation

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V53C8125H30

ULTRA-HIGH PERFORMANCE, 128K X 8 FAST PAGE MODE CMOS DYNAMIC RAM

Mosel Vitelic Corporation  

MOSEL VITELIC

Fast Page Mode provides sustained data rates

up to 53 MHz for applications that require high data

rates such as bit-mapped graphics or high-speed

signal processing. The following equation can be

used to calculate the maximum data rate:

Data Rate = -t-R----C-----+-----22---55----65-----×----t--P----C--

Data Output Operation

The V53C8125H Input/Output is controlled by

OE, CAS, WE and RAS. A RAS low transition en-

ables the transfer of data to and from the selected

row address in the Memory Array. A RAS high tran-

sition disables data transfer and latches the output

data if the output is enabled. After a memory cycle

is initiated with a RAS low transition, a CAS low

transition or CAS low level enables the internal I/O

path. A CAS high transition or a CAS high level dis-

ables the I/O path and the output driver if it is en-

abled. A CAS low transition while RAS is high has

no effect on the I/O data path or on the output driv-

ers. The output drivers, when otherwise enabled,

can be disabled by holding OE high. The OE signal

has no effect on any data stored in the output latch-

es. A WE low level can also disable the output driv-

ers when CAS is low. During a Write cycle, if WE

goes low at a time in relationship to CAS that would

normally cause the outputs to be active, it is neces-

sary to use OE to disable the output drivers prior to

the WE low transition to allow Data In Setup Time

(tDS) to be satisfied.

V53C8125H

Power-On

After application of the VCC supply, an initial

pause of 200 µs is required followed by a minimum

of 8 initialization cycles (any combination of cycles

containing a RAS clock). Eight initialization cycles

are required after extended periods of bias without

clocks (greater than the Refresh Interval).

During Power-On, the VCC current requirement of

the V53C8125H is dependent on the input levels of

RAS and CAS. If RAS is low during Power-On, the

device will go into an active cycle and IDD will exhibit

current transients. It is recommended that RAS and

CAS track with VCC or be held at a valid VIH during

Power-On to avoid current surges.

Table 1. V53C8125H Data Output

Operation for Various Cycle Types

Cycle Type

Read Cycles

CAS-Controlled Write

Cycle (Early Write)

WE-Controlled Write

Cycle (Late Write)

Read-Modify-Write

Cycles

Fast Page Mode

Read

Fast Page Mode Write

Cycle (Early Write)

Fast Page Mode Read-Modify-

Write Cycle

RAS-only Refresh

CAS-before-RAS

Refresh Cycle

CAS-only Cycles

I/O State

Data from Addressed

Memory Cell

High-Z

OE Controlled.

High OE = High-Z I/Os

Data from Addressed

Memory Cell

Data from Addressed

Memory Cell

High-Z

Data from Addressed

Memory Cell

High-Z

Data remains as in

previous cycle

High-Z

V53C8125H Rev. 1.7 August 1998

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