Timing Chart
SFTCLK
Setup/hold time is referred from
rising edge in CLKPOL = GND
falling edge in CLKPOL = VDD
REDxx
GRNxx
BLUxx
H/Vsync
CNTL
DE
Torc
2.0V
0.8V
Tofc
1/Fsftclk
Dsftclk/Fsftclk
Tsetup
Tord
2.0V
0.8V
Tofd
Fig. 6. TTL output timing
Thold
Pixel
Sync/Cntl/DE
SftClk
REFRQP
REFRQN
SDATAP
SDATAN
error
TAclk
Indefinite
Indefinite
TDclk
Fig. 7. Refclk request timing
SDATAP
SDATAN
LOS
TDlos
NRZ data
TAlos
Fig. 8. Idle mode timing
CXB1456R
Vth
–7–