AD7450ARZ-REEL7 查看數據表（PDF） - Analog Devices

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AD7450ARZ-REEL7

Differential Input, 1 MSPS 12-Bit ADC in μSOIC-8 and SO-8

Analog Devices 

AD7450

SINGLE-ENDED OPERATION

When supplied with a 5 V power supply, the AD7450 can handle

a single-ended input. The design of this part is optimized for

differential operation, so with a single-ended input, performance

will degrade. Linearity will typically degrade by 0.2 LSBs, zero

code and full-scale errors will typically degrade by 2 LSBs, and

ac performance is not guaranteed.

To operate the AD7450 in single-ended mode, the VIN+ input is

coupled to the signal source, while the VIN– input is biased to the

appropriate voltage corresponding to the midscale code transi-

tion. This voltage is the common mode, which is a fixed dc

voltage (usually the reference). The VIN+ input swings around

this value and should have voltage span of 2 ϫ VREF to make use

of the full dynamic range of the part. Therefore, the input signal

will have peak-to-peak values of common mode ± VREF. If the

analog input is unipolar then an op amp in a noninverting unity

gain configuration can be used to drive the VIN+ pin. Because

the ADC operates from a single supply, it is necessary to level

shift ground based bipolar signals to comply with the input

requirements. An op amp can be configured to rescale and level

shift the ground based bipolar signal so it is compatible with the

selected input range of the AD7450 (see Figure 18).

+2.5V

0V

–2.5V

R

R

VIN

+

R

–

R

5V

2.5V

0V

VIN+

AD7450

VIN–

VREF

EXTERNAL

VREF (2.5V)

0.1␮F

Figure 18. Applying a Bipolar Single-Ended

Input to the AD7450

SERIAL INTERFACE

Figure 19 shows a detailed timing diagram for the serial interface

of the AD7450. The serial clock provides the conversion clock

and also controls the transfer of data from the AD7450 during

conversion. CS initiates the conversion process and frames the

data transfer. The falling edge of CS puts the track-and-hold into

hold mode and takes the bus out of three-state. The analog input

is sampled and the conversion initiated at this point. The

conversion will require 16 SCLK cycles to complete.

Once 13 SCLK falling edges have occurred, the track-and-hold

will go back into track on the next SCLK rising edge as shown

at Point B in Figure 19. On the 16th SCLK falling edge, the

SDATA line will go back into three-state.

If the rising edge of CS occurs before 16 SCLKs have elapsed,

the conversion will be terminated, and the SDATA line will go

back into three-state. Sixteen serial clock cycles are required to

perform a conversion and to access data from the AD7450. CS

going low provides the first leading zero to be read in by the

microcontroller or DSP. The remaining data is then clocked out

on the subsequent SCLK falling edges beginning with the second

leading zero. Thus, the first falling clock edge on the serial clock

provides the second leading zero. The final bit in the data transfer

is valid on the 16th falling edge, having been clocked out on the

previous (15th) falling edge. Once the conversion is complete

and the data has been accessed after the 16 clock cycles, it is

important to ensure that before the next conversion is initiated,

enough time is left to meet the acquisition and quiet time speci-

fications (see timing examples). To achieve 1 MSPS with an 18

MHz clock for VDD = 5 V, an 18 clock burst will perform the

conversion and leave enough time before the next conversion for

the acquisition and quiet time. This is the same for achieving

833 kSPS with a 15 MHz clock for VDD = 3 V.

In applications with a slower SCLK, it may be possible to read

in data on each SCLK rising edge, i.e., the first rising edge of

SCLK after the CS falling edge would have the leading zero

provided and the 15th SCLK edge would have DB0 provided.

Timing Example 1

Having fSCLK = 18 MHz and a throughput rate of 1 MSPS gives

a cycle time of:

1 Throughput = 1 1,000,000 = 1 µs

A cycle consists of:

( ) t2 + 12.5 1 fSCLK + tACQ = 1 µs

Therefore, if t2 = 10 ns then:

( ) 10 ns + 12.5 1 18 MHz + tACQ = 1 µs

tACQ = 296 ns

This 296 ns satisfies the requirement of 200 ns for tACQ. From

Figure 20, tACQ is comprised of:

( ) 2.5 1 fSCLK + t8 + tQUIET

where t8 = 35 ns. This allows a value of 122 ns for tQUIET, satis-

fying the minimum requirement of 25 ns.

Timing Example 2

Having fSCLK = 5 MHz and a throughput rate of 315 kSPS gives

a cycle time of:

1 Throughput = 1 315,000 = 3.174 µs

A cycle consists of:

( ) t2 + 12.5 1 fSCLK + tACQ = 3.174 µs

Therefore if t2 is 10 ns then:

( ) 10 ns + 12.5 1 5 MHz + tACQ = 3.174 µs

tACQ = 664 ns

This 664 ns satisfies the requirement of 200 ns for tACQ. From

Figure 20, tACQ is comprised of:

( ) 2.5 1 fSCLK + t8 + tQUIET

where t8 = 35 ns. This allows a value of 129 ns for tQUIET, satis-

fying the minimum requirement of 25 ns.

As in this example and with other slower clock values, the signal

may already be acquired before the conversion is complete, but it

is still necessary to leave 25 ns minimum tQUIET between conver-

sions. In Timing Example 2, the signal should be fully acquired

at approximately Point C in Figure 20.

Rev. A

–15–

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