STLC7550TQFP 查看數據表（PDF） - STMicroelectronics

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STLC7550TQFP

LOW POWER LOW VOLTAGE ANALOG FRONT END

STMicroelectronics 

FUNCTIONAL DESCRIPTION (continued)

Figure 1 : Clock Block Diagram

XTALIN

SCLK

(MCLK)

XTALOUT MCM (OCLK)

M/S

STLC7550

VDD

÷M ÷Q

Cont. Reg. : Bit 8-9-10-11-12-13

Sync

% OVER

Bit 3-4-5

FS

Internal

Sampling

4 - MODES OF OPERATION

Thanks to MCM and M/S programmation pins we

can get the following configuration.

Configuration 1 : MCM = 1, M/S = 1

The STLC7550 is in master mode and we have :

Fs = XTAL IN / (M x Q x OVER)

Fs and SCLK are output pins.

Figure 2 : Configuration 1

fQ = 36.864MHz

BCLK

FS

DO

DI

PROCESSOR

XTALIN

SCLK

FS

DIN

DOUT

M/S

MCM

TS

STLC7550

VDD

VDD

GND

The configuration 4 is equivalent to configuration 3

but the Fs is generated and phase controlled by the

processor.

Figure 3 : Configuration 2

fQ = 36.864MHz

BCLK

FS

DO

DI

PROCESSOR

XTALIN

SCLK

M/S

FS

MCM

DIN

DOUT

TS

STLC7550

Figure 4 : Configuration 3 (7546 mode)

fQ = K x Fs

GND

VDD

GND

Configuration 2 : MCM = 1, M/S = 0

The STLC7550 is in slave mode. SCLK is provided

by the STLC7550, the processor generates the Fs

and controls the phase of the sampling frequency.

Fs must be the result of a division of a number of

cycles of SLCK (Fs = SCLK % OVER).

Configuration 3 : MCM = 0, M/S = 1

The STLC7550 is in master mode and the proces-

sor provides the XTAL IN = MCLK = OCLK.

The STLC7550 generates the Fs from OCLK. In

this mode the configuration 3 is equivalent to the

STLC7546 mode.

Configuration 4 : MCM = 0, M/S = 0

The STLC7550 is in slave mode.

BCLK

FS

DO

DI

PROCESSOR

XTALIN

SCLK

FS

DIN

DOUT

M/S

MCM

TS

STLC7550

VDD

GND

GND

Configuration 5 : MCM = 1, M/S = 1 (master codec)

MCM = 0, M/S = 0 (slave codec)

This is dual codec application.

The master codec has his data in timeslot 0 and

the slave codec has his data in timeslot 1 thanks to

the programmation of TS.

7/17

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