T8208 查看數據表（PDF） - Agere -> LSI Corporation

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产品描述 (功能)

比赛名单

T8208

CelXpres™ ATM Interconnect

Agere -> LSI Corporation 

CelXpres T8208

ATM Interconnect

Advance Data Sheet

September 2001

2 Pinout (continued)

Table 3. Cell Bus Pins

Symbol

ua*[4:0]

cb_d*[31:0]

cb_wc*

cb_rc*

cb_fs*

cb_ack*

arb_en*

cb_disable*

cb_iref

cb_vref

cb_vref_vss

cb_gen_wc

cb_gen_rc

Ball

B18, B17, C17, D16,

A18

B5, C6, D7, A5, B6,

C7, A6, B7, A7, C8,

B8, A8, D9, C9, B9,

A9, A11, C11, B11,

A12, B12, C12, D12,

A13, B13, C13, A14,

B14, C14, A15, B15,

D14

A10

B10

C15

B16

A17

C16

A4

D10

C10

A3

B4

Reset

Value

—

Z

—

—

Z

Z

—

—

—

—

—

—

—

Type

Name/Description

I Unit Address Lines (Active-Low). Address assigned to

device for cell bus identification. TTL compatible input,

5 V tolerant.

I/O Cell Bus Data Lines (Active-Low). GTL+ I/O.

I Cell Bus Write Clock (Active-Low). Uses falling edge

to output data on cell bus. Write and read clocks have

the same frequency but different phase. GTL+ input.

I Cell Bus Read Clock (Active-Low). Uses falling edge

to latch data from cell bus. Write and read clocks have

the same frequency but different phase. GTL+ input.

I/O Cell Bus Frame Sync (Active-Low). GTL+ I/O.

I/O Cell Bus Acknowledge Signal (Active-Low). Driven

low on cycle 0 of the following frame when a valid cell is

received from the cell bus. This signal is not driven for

broadcast or multicast cells. GTL+ I/O.

I Cell Bus Arbiter Enable (Active-Low). Cell bus arbiter

enable. Only one device on the cell bus may be config-

ured as arbiter. TTL-compatible input, 5 V tolerant. This

pin has an internal 50 kΩ pull-up resistor.

I Cell Bus Disable (Active-Low). CMOS input that 3-

states all GTL+ outputs when low, but GTL+ buffer inputs

are active. This pin has an internal 50 kΩ pull-up resistor.

I Cell Bus Current Reference. Precision current refer-

ence for GTL+ buffers. A 1 kΩ, 1% resistor must be con-

nected between this pin and GND.

I Cell Bus Voltage Reference. GTL+ buffer threshold

voltage reference (1.0 V typical). This voltage reference

is 2/3 VTT, created using a voltage divider of three 1 kΩ,

1% resistors between VTT and cb_vref_vss.

— Cell Bus Voltage Reference Ground.

O Cell Bus Generated Write Clock. TTL Compatible

(+5 V) driver. 10 mA drive. This is the write clock gener-

ated by the T8208 device. Read/write clock delay set by

register 0122h bits[15:13].

O Cell Bus Generated Read Clock. TTL Compatible

(+5 V) driver. 10 mA drive. This is the read clock gener-

ated by the T8208 device. Read/write clock delay set by

register 0122h bits[15:13].

16

Agere Systems Inc.

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