SN74LS393D(1999) 查看數據表（PDF） - ON Semiconductor

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SN74LS393D
(Rev.:1999)

Dual 4−Stage Binary Counter

ON Semiconductor 

SN74LS393

CONNECTION DIAGRAM DIP (TOP VIEW)

VCC CP MR Q0 Q1 Q2 Q3

14 13 12 11 10 9 8

1234567

CP MR Q0 Q1 Q2 Q3 GND

NOTE:

The Flatpak version

has the same pinouts

(Connection Diagram) as

the Dual In-Line Package.

PIN NAMES

CP

CP0

CP1

MR

Q0 – Q3

Clock (Active LOW Going Edge)

Input to +16 (LS393)

Clock (Active LOW Going Edge)

Input to ÷2 (LS390)

Clock (Active LOW Going Edge)

Input to ÷ 5 (LS390)

Master Reset (Active HIGH) Input

Flip–Flop Outputs

NOTES:

a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.

LOADING (Note a)

HIGH

LOW

0.5 U.L.

0.5 U.L.

0.5 U.L.

0.5 U.L.

10 U.L.

1.0 U.L.

1.0 U.L.

1.5 U.L.

0.25 U.L.

5 U.L.

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