74HC30N 查看數據表（PDF） - NXP Semiconductors.

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比赛名单

74HC30N

8-input NAND gate

NXP Semiconductors. 

NXP Semiconductors

74HC30; 74HCT30

8-input NAND gate

6. Functional description

Table 3. Function table[1]

Input

Output

A

B

C

D

E

F

G

H

Y

L

X

X

X

X

X

X

X

H

X

L

X

X

X

X

X

X

H

X

X

L

X

X

X

X

X

H

X

X

X

L

X

X

X

X

H

X

X

X

X

L

X

X

X

H

X

X

X

X

X

L

X

X

H

X

X

X

X

X

X

L

X

H

X

X

X

X

X

X

X

L

H

H

H

H

H

H

H

H

H

L

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.

7. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

Conditions

Min Max Unit

VCC

IIK

IOK

IO

ICC

IGND

Tstg

Ptot

supply voltage

input clamping current

output clamping current

output current

supply current

ground current

storage temperature

total power dissipation

DIP14 package

VI < 0.5 V or VI > VCC + 0.5 V

VO < 0.5 V or VO > VCC + 0.5 V

0.5 V < VO < VCC + 0.5 V

0.5

[1] -

[1] -

-

-

50

65

+7

V

20 mA

20 mA

25 mA

50

mA

-

mA

+150 C

[2] -

750 mW

SO14, (T)SSOP14 packages

[2] -

500 mW

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C.

For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.

For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.

74HC_HCT30

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 6 — 27 December 2012

© NXP B.V. 2012. All rights reserved.

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