K6R1016C1 查看數據表（PDF） - Samsung
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K6R1016C1 Datasheet PDF : 11 Pages
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K6R1016C1D
PRELIMINARY
CMOS SRAM
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tAA
tCO
CS
tBA
UB, LB
OE
Data out
High-Z
tBLZ(4,5)
tOE
tOLZ
tLZ(4,5)
VCC
ICC
Current
ISB
tPU
50%
Valid Data
tHZ(3,4,5)
tBHZ(3,4,5)
tOHZ
tDH
tPD
50%
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or
VOL levels.
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1) (OE =Clock)
Address
OE
CS
UB, LB
WE
Data in
Data out
tWC
tAW
tCW(3)
tBW
tWR(5)
tAS(4)
tWP(2)
High-Z
tOHZ(6)
tDW
tDH
Valid Data
High-Z
-7-
Rev. 3.0
July 2004
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