CY7C4261V(2003) 查看數據表（PDF） - Cypress Semiconductor

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CY7C4261V
(Rev.:2003)

16K/32K/64K/128K x 9 Low-Voltage Deep Sync™ FIFOs

Cypress Semiconductor 

Switching Waveforms

Write Cycle Timing

WCLK

D0 –D17

WEN1

tCLKH

tCLK

tCLKL

tDS

tENS

WEN2

(if applicable)

FF

RCLK

tWFF

tSKEW1 [12]

REN1, REN2

Read Cycle Timing

RCLK

REN1, REN2

tENS

EF

Q0 –Q17

OE

WCLK

tOLZ

tCLKH

tCKL

tCLKL

tENH

tREF

NO OPERATION

tA

tOE

tSKEW1 [13]

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

tDH

tENH

tWFF

NO OPERATION

NO OPERATION

tREF

VALID DATA

tOHZ

WEN1

WEN2

Notes:

12. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising

edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge.

13. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the rising

edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK rising edge.

Document #: 38-06013 Rev. *A

Page 8 of 16

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