74F521 查看數據表（PDF） - Fairchild Semiconductor
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74F521 Datasheet PDF : 8 Pages
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Unit Loading/Fan Out
Pin Names
Description
A0–A7
B0–B7
IA=B
OA=B
Word A Inputs
Word B Inputs
Expansion or Enable Input (Active LOW)
Identity Output (Active LOW)
U.L.
Input IIH/IIL
HIGH/LOW Output IOH/IOL
1.0/1.0 20 µA/−0.6 mA
1.0/1.0 20 µA/−0.6 mA
1.0/1.0 20 µA/−0.6 mA
50/33.3 −1 mA/20 mA
Truth Table
IA = B
L
L
H
H
H = HIGH Voltage Level
L = LOW Voltage Level
Note 1: A0 = B0, A1 = B1, A2 = B2, etc.
Logic Diagram
Inputs
A, B
A = B (Note 1)
A≠B
A = B (Note 1)
A≠B
Output
OA = B
L
H
H
H
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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