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MC74LVQ573DW 查看數據表(PDF) - Motorola => Freescale

零件编号
产品描述 (功能)
比赛名单
MC74LVQ573DW
Motorola
Motorola => Freescale Motorola
MC74LVQ573DW Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Low-Voltage Quiet CMOS
Octal Transparent Latch
Flow Through Pinout
(3-State, Non-Inverting)
The MC74LVQ573 is a high performance, non–inverting octal
transparent latch operating from a 2.7 to 3.6V supply. The MC74LVQ573
is suitable for TTL level bus oriented applications where a memory
element is required.
The MC74LCX573 contains 8 D–type latches with 3–state standard
outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs
enters the latches. In this condition, the latches are transparent, i.e., a
latch output will change state each time its D input changes. When LE is
LOW, the latches store the information that was present on the D inputs a
setup time preceding the HIGH–to–LOW transition of LE. The 3–state
standard outputs are controlled by the Output Enable (OE) input. When
OE is LOW, the standard outputs are enabled. When OE is HIGH, the
standard outputs are in the high impedance state, but this does not
interfere with new data entering into the latches. The LCX573 flow
through design facilitates easy PC board layout.
Designed for 2.7 to 3.6V VCC Operation – Ideal for Low Power/Low
Noise Applications
Guaranteed Simultaneous Switching Noise Level and Dynamic
Threshold Performance
Guaranteed Skew Specifications
Guaranteed Incident Wave Switching into 75
Low Static Supply Current (10µA) Substantially Reduces System Power
Requirements
Latchup Performance Exceeds 500mA
ESD Performance: Human Body Model >2000V
Pinout: 20–Lead (Top View)
VCC O0 O1 O2 O3 O4 O5 O6 O7 LE
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
OE D0 D1 D2 D3 D4 D5 D6 D7 GND
MC74LVQ573
LVQ
LOW–VOLTAGE
CMOS OCTAL
TRANSPARENT LATCH
20
1
20
1
20
1
20
1
DW SUFFIX
PLASTIC SOIC
CASE 751D–04
M SUFFIX
PLASTIC SOIC EIAJ
CASE 967–01
SD SUFFIX
PLASTIC SSOP
CASE 940C–03
DT SUFFIX
PLASTIC TSSOP
CASE 948E–02
PIN NAMES
Pins
Function
OE
LE
D0–D7
O0–O7
Output Enable Input
Latch Enable Input
Data Inputs
3–State Latch Outputs
11/95
© Motorola, Inc. 1995
1
REV 0

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