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SAF7113H

9-bit video input processor

NXP Semiconductors. 

Philips Semiconductors

SAF7113H

9-bit video input processor

ANALOG INPUT

ADC

NO BLANKING ACTIVE

1

0

VBLK

<- CLAMP

1

0

HCL

GAIN ->

1

0

HSY

1

0

< CLL

0

1

< SBOT

1

0

> WIPE

+ CLAMP

− CLAMP NO CLAMP + GAIN

WIPE = white peak level (254);

SBOT = sync bottom level (1);

CLL = clamp level [60 Y (128 C)];

HSY = horizontal sync pulse;

HCL = horizontal clamp pulse.

Fig 8. Clamp and gain flow

− GAIN fast − GAIN

slow + GAIN

mgc647

8.3 Chrominance processing

The 9-bit chrominance signal is fed to the multiplication inputs of a quadrature

demodulator, where two subcarrier signals from the local oscillator DTO1 are applied (0°

and 90° phase relationship to the demodulator axis). The frequency is dependent on the

present color standard. The output signals of the multipliers are low-pass filtered (four

programmable characteristics) to achieve the desired bandwidth for the color difference

signals (PAL and NTSC) or the 0° and 90° FM signals (SECAM).

The color difference signals are fed to the Brightness/Contrast/Saturation block (BCS),

which includes the following five functions:

• Automatic Gain Control (AGC) for chrominance PAL and NTSC

• Chrominance amplitude matching (different gain factors for (R − Y) and (B − Y) to

achieve ITU-R BT 601 levels CR and CB for all standards)

• Chrominance saturation control

• Luminance contrast and brightness

• Limiting YUV to the values 1 (minimum) and 254 (maximum) to fulfil ITU-R BT 601

requirements.

9397 750 14231

Product data sheet

Rev. 03 — 9 May 2005

© Koninklijke Philips Electronics N.V. 2005. All rights reserved.

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