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AN-8027

FAN480X PFC+PWM Combination Controller Application

Fairchild Semiconductor 

AN-8027

[STEP-1] Define System Specifications

Since the overall system is comprised of two stages (PFC

and DC/DC), as shown in Figure 12, the input power and

output power of the boost stage are given as:

P

P = OUT

IN

η

(8)

P

P

= OUT

BOUT

η PWM

(9)

where η is the overall efficiency and ηPWM is the forward

converter efficiency.

The nominal output current of boost PFC stage is given as:

P

I=

OUT

η V BOUT

PWM BOUT

PIN

PBOUT

IBOUT

(10)

POUT

Boost

PFC

VBOUT Forward

DC/DC

VOUT

(Design Example) Since the switching frequency is

65kHz, CT is selected as 1nF. Then the maximum duty

cycle of PFC gate drive signal is obtained as:

DMAX .PFC = 1 − 360 ⋅ CT ⋅ fSW = 0.98

The timing resistor is determined as:

RT

=1⋅ 1

4 0.56 fSW CT

= 6.9kΩ

[STEP-3] Line Sensing Circuit Design

FAN480X senses the RMS value and instantaneous value of

line voltage using the VRMS and IAC pins, respectively, as

shown in Figure 13. The RMS value of the line voltage is

obtained by an averaging circuit using low pass filter with

two poles. Meanwhile, the instantaneous line voltage

information is obtained by sensing the current flowing into

IAC pin through RIAC.

VIN

IL

Figure 12. Two Stage Configuration

(Design Example)

P 300

P = = OUT

= 366W

IN η 0.82

P

300

P = = OUT

= 349W

BOUT

η PWM

0.86

I BOUT

=

P

OUT

V ηPWM BOUT

= 300 = 0.9 A

0.86 ⋅ 387

[STEP-2] Frequency Setting

The switching frequency is determined by the timing resistor

and capacitor (RT and CT) as:

fSW

≅

1⋅

1

4 0.56 ⋅ RT

⋅ CT

(11)

It is typical to use a 470pF~1nF capacitor for 50~75kHz

switching frequency operation since the timing capacitor

value determines the maximum duty cycle of PFC gate drive

signal as:

DMAX .PFC

=

1

−

TOFF

MIN

.

TSW

= 1− 360 ⋅ CT ⋅ fSW

(12)

RRMS1

IAC

RIAC

CRMS1

CRMS2

RRMS2

IA

C

VRMS

RRMS3

VRMS

VIN

120/100Hz

fp1

fp2

Figure 13. Line Sensing Circuits

RMS sensing circuit should be designed considering the

nominal operation range of line voltage and brownout

protection trip point as:

π VRMS −UVL

= VLINE.BO

2RRMS 3

RRMS1 + RRMS 2 + RRMS 3

⋅2

VRMS −UVH

< VLINE.MIN

2RRMS 3

RRMS1 + RRMS 2 + RRMS 3

(13)

(14)

where VRMS-UVL and VRMS-UVH are the brown OUT/IN

thresholds of VRMS.

It is typical to set RRMS2 as 10% of RRMS1. The poles of the

low pass filter are given as:

f P1

≅

2π

1

⋅ CRMS1

⋅ RRMS 2

fP2

≅

2π

1

⋅ CRMS 2

⋅ RRMS 3

(15)

(16)

© 2009 Fairchild Semiconductor Corporation

Rev. 1.0.0 • 8/26/09

6

www.fairchildsemi.com

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