74HCT563 查看數據表（PDF） - Renesas Electronics
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74HCT563 Datasheet PDF : 10 Pages
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HD74HCT563, HD74HCT573
Octal Transparent Latches (with 3-state outputs)
REJ03D0669–0200
(Previous ADE-205-559)
Rev.2.00
Mar 30, 2006
Description
When the latch enable (LE) input is high, the Q outputs of HD74HCT563 will follow the inversion of the D inputs and
the Q outputs of HD74HCT573 will follow the D inputs. When the latch enable goes low, data at the D inputs will be
retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control
input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of
the storage elements.
Features
• LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility
• High Speed Operation: tpd (Data to Q, Q) = 13 ns typ (CL = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads
• Wide Operating Voltage: VCC = 4.5 to 5.5 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74HCT573P
DILP-20 pin
PRDP0020AC-B
(DP-20NEV)
P
HD74HCT563FPEL
HD74HCT573FPEL
SOP-20 pin (JEITA)
PRSP0020DD-B
(FP-20DAV)
FP
PRSP0020DC-A
HD74HCT563RPEL SOP-20 pin (JEDEC) (FP-20DBV)
RP
HD74HCT573TELL TSSOP-20 pin
PTSP0020JB-A
T
(TTP-20DAV)
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
EL (1,000 pcs/reel)
ELL (2,000 pcs/reel)
Function Table
Inputs
Outputs
Output Control
Latch Enable
Data
HD74HCT563
HD74HCT573
L
H
H
L
H
L
H
L
H
L
L
L
X
Q0
Q0
H
X
X
Z
Z
Q0 : level of Q before the indicated Steady-sate input conditions were established.
Q0 : complement of Q0 or level of Q before the indicated Steady-state input conditions were established.
Rev.2.00, Mar 30, 2006 page 1 of 9
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