MK1412A 查看數據表（PDF） - Integrated Circuit Systems
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MK1412A Datasheet PDF : 4 Pages
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Pin Assignment
X1
VDD
GND
CLK/2
1
8 X2
2
7 CLK
3
6 S1
4
5 S0
8 pin SOIC
MK1412
MPEG Audio Clock Synthesizer
Audio Clock Outputs Select Table (MHz)
S1 S0
00
01
10
11
CLK
16.384
22.5792
24.576
49.152
CLK/2
8.192
11.2896
12.288
24.576
Accuracy
1 ppm
25 ppm
1 ppm
1 ppm
Pin Descriptions
Number
1
2
3
4
5
6
7
8
Name
X1
VDD
GND
CLK/2
S0
S1
CLK
X2
Type Description
I Crystal Connection. Connect to a 14.31818 MHz crystal or clock.
P Connect to +3.3V or +5V.
P Connect to ground.
O Audio Clock divide by 2 output as per table above.
I Frequency Select 0 Input. Determines CLK and CLK/2 outputs as per table above.
I Frequency Select 0 Input. Determines CLK and CLK/2 outputs as per table above.
O Audio Clock output as per table above.
O Crystal Connection to a 14.31818 MHz crystal, or leave unconnected for clock input.
Key: I = Input, O = output, P = power supply connection
External Components/Crystal Selection
A minimum number of external components are required for proper oscillation. For a crystal input, one
load capacitor can be connected to each of the X1 and X2 pins and ground, and a parallel resonant
14.31818 MHz crystal is recommended. The value (in pF) of each crystal load capacitor should equal
(CL-18)*2, where CL is the crystal’s load (correlation) capacitance in pF. So for crystals with 18 pF load
capacitance (or less), no extra capacitors are needed. The frequency tolerance of the crystal should be
50ppm or better. For a clock input, connect to X1 and leave X2 unconnected. A decoupling capacitor of
0.1µF should be connected between VDD and GND on pins 2 and 3, and 33Ω terminating resistor may
be used on the clock outputs if the trace is longer than 1 inch.
MDS 1412 B
2
Revision 060200
Printed 11/15/00
Integrated Circuit Systems, Inc.• 525 Race Street• San Jose • CA • 95126• (408)295-9800tel •www.icst.com
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