UT62L1024BS-70LLI(Rev0_1) 查看數據表（PDF） - Utron Technology Inc
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UT62L1024BS-70LLI Datasheet PDF : 14 Pages
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UTRON
Preliminary Rev. 0.1
UT62L1024(I)
128K X 8 BIT LOW POWER CMOS SRAM
AC ELECTRICAL CHARACTERISTICS (VCC = 2.5V~3.6V , TA = -40℃~+85℃ )
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
SYMBOL
tRC
tAA
tACE1, tACE2
tOE
tCLZ1*, tCLZ2*
tOLZ*
tCHZ1*, tCHZ2*
tOHZ*
tOH
UT62L1024-55
MIN.
MAX.
55
-
-
55
-
55
-
30
10
-
5
-
-
30
-
30
5
-
UT62L1024-70
MIN.
MAX.
70
-
-
70
-
70
-
35
10
-
5
-
-
35
-
35
5
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2) WRITE CYCLE
PARAMETER
SYMBOL
UT62L1024-55
MIN.
MAX.
Write Cycle Time
tWC
55
-
Address Valid to End of Write
tAW
50
-
Chip Enable to End of Write
tCW1, tCW2
50
-
Address Set-up Time
tAS
0
-
Write Pulse Width
tWP
40
-
Write Recovery Time
tWR
0
-
Data to Write Time Overlap
tDW
25
-
Data Hold from End of Write-Time tDH
0
-
Output Active from End of Write
tOW*
5
-
Write to Output in High-Z
tWHZ*
-
20
*These parameters are guaranteed by device characterization, but not production tested.
UT62L1024-70
MIN.
MAX.
70
-
60
-
60
-
0
-
45
-
0
-
30
-
0
-
5
-
-
25
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
P80078
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