UT62L1024SC-55LLI 查看數據表（PDF） - Utron Technology Inc

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UT62L1024SC-55LLI

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Utron Technology Inc 



Rev. 1.1

UTRON

UT62L1024(I)

128K X 8 BIT LOW POWER CMOS SRAM

DATA RETENTION CHARACTERISTICS (TA = - 40℃ to 85℃)

PARAMETER

Vcc for Data Retention

Data Retention Current

Chip Disable to Data

Retention Time

Recovery Time

tRC* = Read Cycle Time

SYMBOL

VDR

IDR

tCDR

tR

TEST CONDITION

MIN.

CE ≧VCC-0.2V

1.5

or CE2≦0.2V

Vcc=1.5V

CE ≧VCC-0.2V

or CE2≦0.2V

-L -

- LL -

See Data Retention

Waveforms (below)

0

tRC*

TYP. MAX. UNIT

-

3.6

V

10 80 µA

1

6

µA

-

-

ns

-

-

ns

DATA RETENTION WAVEFORM

Low Vcc Data Retention Waveform (1) ( CE controlled)

VCC

CE

Vcc(min.)

tCDR

VIH

VDR ≧ 1.5V

CE ≧ VCC-0.2V

Vcc(min.)

tR

VIH

Low Vcc Data Retention Waveform (2) (CE2 controlled)

VCC

CE2

VCC(min.)

tCDR

VIL

VDR ≧ 1.5V

CE2 ≦ 0.2V

VCC(min.)

tR

VIL

UTRON TECHNOLOGY INC.

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882 FAX: 886-3-5777919

8

P80078

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