LP62S2048A-T 查看數據表（PDF） - AMIC Technology

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LP62S2048A-T

256K X 8 BIT LOW VOLTAGE CMOS SRAM

AMIC Technology 

AC Test Conditions

Input Pulse Levels

Input Rise and Fall Time

Input and Output Timing Reference Levels

Output Load

LP62S2048A-T Series

0.4V to 2.4V

5 ns

1.5V

See Figures 1 and 2

TTL

TTL

CL

30pF

CL

5pF

* Including scope and jig.

* Including scope and jig.

Figure 1. Output Load

Data Retention Characteristics (TA = -25°C to 85°C)

Figure 2. Output Load for tCLZ1,

tCLZ2, tOHZ, tOLZ, tCHZ1,

tCHZ2, tWHZ, and tOW

Symbol

Parameter

Min.

Max.

Unit

Conditions

VDR1

VDR2

VCC for Data Retention

2.0

3.3

V

CE1 ≥ VCC - 0.2V

2.0

3.3

V

CE2 ≤ 0.2V,

ICCDR1

Data Retention Current

ICCDR2

VCC = 2.0V,

-

5**

µA

CE1 ≥ VCC - 0.2V,

VIN ≥ 0V

-

5**

VCC = 2.0V,

µA

CE2 ≤ 0.2V,

VIN ≥ 0V

tCDR

Chip Disable to Data Retention Time

0

tR

Operation Recovery Time

tRC

tVR

VCC Rising Time from Data Retention Voltage

5

to Operating Voltage

-

ns

-

ns

See Retention Waveform

-

ms

** LP62S2048A-55LLT/70LLT ICCDR: max. 1µA at TA = 0°C to + 40°C

PRELIMINARY (June, 2002, Version 0.0)

12

AMIC Technology, Inc.

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