A14100 查看數據表（PDF） - Microsemi Corporation
零件编号
产品描述 (功能)
比赛名单
A14100 Datasheet PDF : 90 Pages
| |||
2 – Detailed Specifications
This section of the datasheet is meant to familiarize the user with the architecture of the ACT 3 family of
FPGA devices. A generic description of the family will be presented first, followed by a detailed
description of the logic blocks, the routing structure, the antifuses, and the special function circuits. The
on-chip circuitry required to program the devices is not covered.
Topology
The ACT 3 family architecture is composed of six key elements: Logic modules, I/O modules, I/O Pad
Drivers, Routing Tracks, Clock Networks, and Programming and Test Circuits. The basic structure is
similar for all devices in the family, differing only in the number of rows, columns, and I/Os. The array
itself consists of alternating rows of modules and channels. The logic modules and channels are in the
center of the array; the I/O modules are located along the array periphery. A simplified floor plan is
depicted in Figure 2-1.
An Array with n rows and m columns
0 1 234 5
Rows Channels
c–1
c c+1
m m+1 m+2 m+3
n+2
Columns
n+1
IO IO IO CLKM
IO IO IO IO IO IO
Top I/Os
n+1
n
IO IO BIN S S C C S
S C C S C S IO IO
n
n–1
IO IO BIN S S C C S
•
•
n–1
•
•
2
• IO IO BIN S S C C S
•
2
1
IO IO BIN S S C C S
S C C S C S IO IO
S C C S C S IO IO
S C C S C S IO IO
1
Left I/Os
Right I/Os
0
BIO IO IO IO IO IO
IO IO IO IO IO IO
Bottom I/Os
0
Figure 2-1 • Generalized Floor Plan of ACT 3 Device
Revision 3
2-1
Share Link: 