MAX4754 查看數據表（PDF） - Maxim Integrated
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MAX4754 Datasheet PDF : 15 Pages
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0.5Ω, Quad SPDT Switches in UCSP/QFN
Timing Circuits/Timing Diagrams
MAX4754/MAX4754A
MAX4755/MAX4756/
MAX4756A
VN_
NO_
OR NC_
LOGIC
INPUT
IN_
GND
V+
V+
COM_
RL
VOUT
CL
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
( ) VOUT = VN_
RL
RL + RON
Figure 1. Switching Time
V+
LOGIC
INPUT 0V
50%
tr < 5ns
tf < 5ns
50%
SWITCH 0V
OUTPUT
tOFF
VOUT 0.9 x V0UT
0.9 x VOUT
tON
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
MAX4754/MAX4754A
MAX4755/MAX4756/
MAX4756A
NC_
VN_
NO_
V+
V+
COM_
LOGIC
INPUT
IN_
GND
VOUT
RL
CL
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
Figure 2. Break-Before-Make Interval
V+
LOGIC
INPUT
50%
0V
VOUT
0.9 x VOUT
tBBM
MAX4754/MAX4754A
MAX4755/MAX4756/
MAX4756A
RGEN
VGEN
NC_
OR NO_
GND
V+
V+
COM_
IN_
VIL TO VIH
Figure 3. Charge Injection
VOUT
CL
VOUT
IN
OFF
ΔVOUT
OFF
ON
ON
OFF
OFF
IN
Q = (ΔVOUT)(CL)
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
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