SM5878AM 查看數據表（PDF） - Nippon Precision Circuits

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比赛名单

SM5878AM

3rd-order Σ∆, 2-channel D/A converter

Nippon Precision Circuits  

BLOCK DIAGRAM

SM5878AM/AV

LRCI

BCKI

DI

MODE

ATCK

MUTE

RSTN

DS

DVSS

DVDD

TSTN

TO1

Attenuation

counter

Timing

control

Input interface

L

R

Filter & attenuation

operation block

L

R

Noise shaper

operation block

MUTEO

DEEM

CKO

XVSS

XTO

XTI

XVDD

AVDDL

11Level

DEM DAC

11Level

DEM DAC

11Level

DEM DAC

11Level

DEM DAC

AVDDR

−+

LO

AVSS

RO

PIN DESCRIPTION

Number

1

2

3

4

5

6

7

8

9

Name

MUTE

DEEM

CKO

DVSS

BCKI

DI

DVDD

LRCI

TSTN

I/O

Description

Ip

When MODE is HIGH: Soft mute ON/OFF control. Mute is active when HIGH.

When MODE is LOW: Attenuator level direction control. The attenuator direction is down when HIGH.

Ip Deemphasis control. Deemphasis is ON when HIGH, and OFF when LOW.

O 16.9344 MHz clock output

- Digital ground

Ip Bit clock input

Ip Serial data input

- Digital supply

Ip

Input sample data rate (fs) clock input pin. Left-channel input when HIGH, and right-channel input when

LOW.

Ip Test pin. Test mode when LOW.

NIPPON PRECISION CIRCUITS—3

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