LC865508A 查看數據表（PDF） - SANYO -> Panasonic
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LC865508A
SANYO -> Panasonic
LC865508A Datasheet PDF : 19 Pages
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LC865520A/16A/12A/08A/04A
2. Recommended Operating Range at Ta=-30°C to +70°C, VSS=0V
Parameter
Operating
Supply
voltage
Symbol
VDD(1)
VDD(2)
Hold voltage VHD
Input high
voltage
VIH(1)
VIH(2)
VIH(3)
VIH(4)
VIH(5)
Input low
voltage
VIH(6)
VIH(7)
VIL(1)
VIL(2)
VIL(3)
VIL(4)
VIL(5)
VIL(6)
Operation
cycle time
Oscillation
frequency
range
(Note 1)
tCYC
FmCF(1)
FmCF(2)
FmRC
FsXtal
Ratings
Pins
Conditions
unit
VDD[V] min. typ. max.
VDD
0.98µs ≤ tCYC
tCYC ≤ 400µs
4.5
6.0 V
3.9µs ≤ tCYC
tCYC ≤ 400µs
2.5
6.0
VDD
RAMs and the
2.0
6.0
registers hold
voltage at HOLD
mode.
Port 0 at CMOS output Output disable
2.5 to 6.0 0.33VDD
VDD
+1.0
Port 0 at N-ch open drain Output disable
4.0 to 6.0 0.75VDD
13.5
output
2.5 to 4.0 0.8VDD
13.5
•Port 1
Output disable
2.5 to 6.0 0.75VDD
VDD
•Ports 72,73
•Port 3 at CMOS
output
Port 3 at N-ch open
Output disable
4.5 to 6.0 0.75VDD
13.5
drain output
2.5 to 4.0 0.8VDD
13.5
•Port 70
Output disable
2.5 to 6.0 0.75VDD
VDD
Port input/interrupt
•Port 71
• RES
Port 70
Output disable
2.5 to 6.0 0.9VDD
VDD
Watchdog timer
•Port 8
•Output disable 2.5 to 6.0 0.75VDD
VDD
•Ports 74 ,75
•Using as port
Port 0 at CMOS
Output disable
2.5 to 6.0 VSS
0.2VDD
output option
Port 0 at N-ch open
Output disable
2.5 to 6.0 VSS
0.25VDD
drain output
•Ports 1,3
Output disable
2.5 to 6.0 VSS
0.25VDD
•Ports 72,73
•Port 70
Output disable
2.5 to 6.0 VSS
0.25VDD
Port input/interrupt
•Port 71
• RES
Port 70
Output disable
2.5 to 6.0 VSS
0.8VDD
Watchdog timer
-1.0
•Port 8
•Output disable 2.5 to 6.0 VSS
0.25VDD
•Ports 74 ,75
•Using as port
4.5 to 6.0 0.98
400 µs
2.5 to 6.0 3.9
400
CF1, CF2
•6MHz
4.5 to 6.0 5.88 6 6.12 MHz
(ceramic resonator
oscillation)
•Refer to figure 1
CF1, CF2
•3MHz
2.5 to 6.0 2.94 3 3.06
(ceramic resonator
oscillation)
•Refer to figure 1
RC oscillation
2.5 to 6.0 0.3 0.8 3.0
XT1, XT2
•32.768kHz
2.5 to 6.0
32.768
kHz
(crystal oscillation)
•Refer to figure 2
Continue.
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