AK4550VT 查看數據表（PDF） - Asahi Kasei Microdevices

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AK4550VT

Low Power & Small Package 16bit ∆Σ CODEC

Asahi Kasei Microdevices 

ASAHI KASEI

[AK4550]

SYSTEM DESIGN

Figure 3 shows the system connection diagram. An evaluation board[AKD4550] is available which demonstrates

application circuit, optimum layout, power supply arrangements and measurement results.

Rch In

470

+

2.2n

Lch In

470

+

2.2n

Analog Supply

2.3 ∼ 3.6V

10u +

+

4.7u

0.1u

1 VCOM

AOUTR 16

2 AINR

AOUTL 15

3

4

0.1u

5

AINL

VSS

VDD

AK4550 PWDA 14

PWAD 13

Top View SCLK 12

6 DEM0

MCLK 11

7 DEM1

LRCK 10

8 SDTO

SDTI 9

Reset

Reset

Controller

Mode

Control

Analog Ground

System Ground

Figure 3. System Connection Diagram Example

Notes:

- LRCK=fs, 32fs ≤ SCLK ≤ 96fs, MCLK=256fs/384fs/512fs.

- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive

load.

- Electrolytic capacitor value of VCOM depends on low frequency noise of supply voltage.

M0068-E-01

- 11 -

2000/4

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