CY7C146(2005) 查看數據表（PDF） - Cypress Semiconductor

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CY7C146
(Rev.:2005)

2K x 8 Dual-Port Static RAM

Cypress Semiconductor 

Switching Waveforms (continued)

Busy Timing Diagram No. 3 (Write with BUSY, Slave: CY7C142/CY7C146)

CE

R/W

tWB

BUSY

tPWE

tWH

CY7C132/CY7C136

CY7C142/CY7C146

Interrupt Timing Diagrams[18]

Left Side Sets INTR:

ADDRESSL

CEL

tWC

WRITE 7FF

tINS

tHA

R/WL

INTR

tEINS

tSA

tWINS

Right Side Clears INTR:

ADDRESSR

CER

R/WR

tHA

tEINR

OER

INTR

Right Side Sets INTL:

ADDRESSR

CER

R/WR

INTL

tWC

WRITE 7FE

tINS

tHA

tEINS

tSA

tWINS

tRC

READ 7FF

tINR

tOINR

Document #: 38-06031 Rev. *C

Page 10 of 18

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