MC10H109 查看數據表（PDF） - ON Semiconductor
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MC10H109 Datasheet PDF : 4 Pages
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MC10H109
Dual 4-5-Input OR/NOR
Gate
The MC10H109 is a dual 4–5–input OR/NOR gate. This MECL
10H part is a functional/pinout duplication of the standard MECL 10K
family part, with 100% improvement in propagation delay, and no
increase in power–supply current.
• Propagation Delay, 1.0 ns Typical
• Power Dissipation 35 mW/Gate Typical (same as MECL 10K)
• Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K–Compatible
LOGIC DIAGRAM
4
5
3
6
2
7
9
10
11
14
12
15
13
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
DIP
PIN ASSIGNMENT
VCC1
1
AOUT
2
AOUT
3
AIN
4
AIN
5
AIN
6
AIN
7
VEE
8
16
VCC2
15
BOUT
14
BOUT
13
BIN
12
BIN
11
BIN
10
BIN
9
BIN
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
http://onsemi.com
CDIP–16
L SUFFIX
CASE 620
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
MARKING
DIAGRAMS
16
MC10H109L
AWLYYWW
1
16
MC10H109P
AWLYYWW
1
1
10H109
AWLYYWW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC10H109L
CDIP–16
25 Units/Rail
MC10H109P
PDIP–16
25 Units/Rail
MC10H109FN PLCC–20
46 Units/Rail
© Semiconductor Components Industries, LLC, 2000
1
March, 2000 – Rev. 6
Publication Order Number:
MC10H109/D
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