ISL59444 查看數據表（PDF） - Renesas Electronics
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ISL59444 Datasheet PDF : 13 Pages
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ISL59444
Application Information
General
The ISL59444 is a 4:1 mux that is ideal as a matrix element in
high performance switchers and routers. The ISL59444 is
optimized to drive a 2pF in parallel with a 500Ω load. The
capacitance can be split between the PCB capacitance an and
external load capacitance. Their low input capacitance and high
input resistance provide excellent 50Ω or 75Ω terminations.
Capacitance at the Output
The output amplifier is optimized for capacitance to ground (CL)
directly on the output pin. Increased capacitance causes higher
peaking with an increase in bandwidth. The optimum range for
most applications is ~1.0pF to ~6pF. The optimum value can be
achieved through a combination of PC board trace capacitance
(CT) and an external capacitor (COUT). A good method to maintain
control over the output pin capacitance is to minimize the trace
length (CT) to the next component, and include a discrete surface
mount capacitor (COUT) directly at the output pin.
For large signal applications where overshoot is important the
circuit in Figure 24B should be used. The series resistor (RS) and
capacitor (CL) form a low pass network that limits system
bandwidth and reduces overshoot. The component values shown
result in a typical pulse response shown in Figure 20.
Ground Connections
For the best isolation and crosstalk rejection, the GND pin and
NIC pins must connect to the GND plane. The NIC pins are placed
on both sides of the input pins. These pins are not internally
connected to the die. It is recommended this pin be tied to
ground to minimize crosstalk.
Control Signals
S0, S1, HIZ - These pins are, TTL/CMOS compatible control
inputs. The S0, S1 pins select which one of the inputs connect to
the output. The HIZ pin is used to three-state the output
amplifiers. For control signal rise and fall times less than 10ns
the use of termination resistors close to the part will minimize
transients coupled to the output.
HIZ State
An internal pull-down resistor connected to the HIZ pin ensures
the device will be active with no connection to the HIZ pin. The
HIZ state is established within approximately 30ns by placing a
logic high (>2V) on the HIZ pin. If the HIZ state is selected, the
output is a high impedance 1.4MΩ. Use this state to control the
logic when more than one mux shares a common output.
In the HIZ state the output is three-stated, and maintains its high
Z even in the presence of high slew rates. The supply current
during this state is basically the same as the active state.
Latch State
The latched control signals allow for synchronized channel switching.
When LE1 is low the master control latch loads the next switching
address (S0, S1), while the closed (assuming LE2 is the inverse of
LE1) slave control latch maintains the current state. LE2 switching
low closes the master latch (with previous assumption), loads the
FN7451 Rev 3.00
August 16, 2012
now open slave latch, and switches the crosspoint to the newly
selected channel. Channel selection is asynchronous (changes with
any control signal change) if both LE1 and LE2 are low.
Power-Up Considerations
The ESD protection circuits use internal diodes from all pins the
V+ and V- supplies. In addition, a dv/dt triggered clamp is
connected between the V+ and V- pins, as shown in the
Equivalent Circuits 1 through 4 section of the “Pin Descriptions”
on page 2. The dv/dt triggered clamp imposes a maximum
supply turn-on slew rate of 1V/µs. Damaging currents can flow
for power supply rates-of-rise in excess of 1V/µs, such as during
hot plugging. Under these conditions, additional methods should
be employed to ensure the rate of rise is not exceeded.
Consideration must be given to the order in which power is
applied to the V+ and V- pins, as well as analog and logic input
pins. Schottky diodes (Motorola MBR0550T or equivalent)
connected from V+ to ground and V- to ground (Figure 25) will
shunt damaging currents away from the internal V+ and V- ESD
diodes in the event that the V+ supply is applied to the device
before the V- supply.
If positive voltages are applied to the logic or analog video input
pins before V+ is applied, current will flow through the internal
ESD diodes to the V+ pin. The presence of large decoupling
capacitors and the loading effect of other circuits connected to
V+, can result in damaging currents through the ESD diodes and
other active circuits within the device. Therefore, adequate
current limiting on the digital and analog inputs is needed to
prevent damage during the time the voltages on these inputs are
more positive than V+.
Limiting the Output Current
No output short circuit current limit exists on these parts. All
applications need to limit the output current to less than 50mA.
Adequate thermal heat sinking of the parts is also required.
Page 11 of 13
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