ICS9148-37 查看數據表（PDF） - Integrated Circuit Systems
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ICS9148-37 Datasheet PDF : 16 Pages
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ICS9148 - 37
Pin Descriptions
PIN NUMBER
1
2
3,9,16,22,27,
33,39,45
4
PIN NAME
VDD1
REF0
CPU3.3#_2.51 ,2
GND
X1
5
6,14
7
8
10, 11, 12, 13
15, 47
17
X2
VDD2
PCICLK_F
FS11 , 2
PCICLK0
FS21 , 2
PCICLK(1:4)
AGP (0:1)
CPU_STOP#1
SDRAM 11
PCI_STOP#1
18
SDRAM 10
20, 21,28, 29, 31,
32, 34, 35,37,38
SDRAM (0:9)
19,30,36
23
24
25
26
40, 41, 43, 44
42
46
48
VDD3
SDATA
SCLK
24MHz
MODE1 , 2
48MHz
FS01 , 2
CPUCLK(0:3)
VDDL
REF1
SD_SEL
VDD4
TYPE
PWR
OUT
IN
PWR
IN
OUT
PWR
OUT
IN
OUT
IN
OUT
OUT
IN
OUT
IN
OUT
OUT
PWR
IN
IN
OUT
IN
OUT
IN
OUT
PWR
OUT
IN
PWR
DESCRIPTION
Ref (0:2), XTAL power supply, nominal 3.3V
14.318 MHz reference clock.
Indicates whether VDDL2 is 3.3V or 2.5V. High=2.5V CPU, LOW=3.3V
CPU1 . Latched input2
Ground
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V
Free running PCI clock output. Synchronous with CPUCLKs with 1-4ns skew
(CPU early) This is not affected by PCI_STOP#
Frequency select pin. Latched Input. Along with other FS pins determines the
CPU, SDRAM, PCI & AGP frequencies.
PCI clock output. Synchronous CPUCLKs with 1-4ns skew (CPU early)
Frequency select pin. Latched Input Along with other FS pins determines the
CPU, SDRAM, PCI & AGP frequencies.
PCI clock outputs. Synchronous CPUCLKs with 1-4ns skew (CPU early)
Advanced Graphic Port outputs, powered by VDD4.
This asynchronous input halts CPUCLK (0:3) and AGP (0:1) clocks at logic 0
level, when input low (in Mobile Mode, MODE=0)
SDRAM clock output. Frequency is selected by the SD_SEL latched input.
SD_SEL = 1 at power on causes SDRAM frequency = CPU frequency
SD_SEL = 0 at power on causes SDRAM frequency = AGP frequency
This asynchronous input halts PCICLK(0:5) clocks at logic 0 level, when
input low (In mobile mode, MODE=0)
SDRAM clock output. Frequency is selected by the SD_SEL latched input.
SD_SEL = 1 at power on causes SDRAM frequency = CPU frenquency
SD_SEL = 0 at power on causes SDRAM frequency = AGP frequency
SDRAM clock outputs. Frequency is selected by the SD_SEL latched input.
SD_SEL = 1 at power on causes SDRAM frequency = CPU frequency
SD_SEL = 0 at power on causes SDRAM frequencies = AGP frequency
Supply for SDRAM (0:11), CPU Core and 24, 48MHz clocks,
nominal 3.3V.
Data input for I2 C serial input.
Clock input of I2 C input
24MHz output clock, for Super I/O timing.
Pin 17, pin 18 function select pin, 1=Desktop Mode, 0=Mobile Mode.
Latched Input.
48MHz output clock, for USB timing.
Frequency select pin. Latched Input Along with other FS pins determines the
CPU, SDRAM, PCI & AGP frequencies.
CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low
Supply for CPU (0:3), either 2.5V or 3.3V nominal
14.318MHz reference clock.
Latched input at Power On selects either CPU (SDSEL=1) or AGP
(SD_SEL=0) frequencies for the SDRAM clock outputs.
Supply for AGP (0:1)
Notes:
1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to
program logic Hi to VDD or GND for logic low.
2
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