µPD70208H, 70216H
1. PIN FUNCTIONS
1.1 LIST OF PIN FUNCTIONS
Pin Name
AD0 to AD15Note 1, 3
AD0 to AD7Note 2, 3
A8 to A15Note 2, 3
A16/PS0 to A19/PS3Note 3
REFRQ
HLDRQ
HLDAK
RESET
RESOUT
READY
NMI
MRDNote 3
MWRNote 3
IORDNote 3
IOWRNote 3
ASTB
UBENote 1, 3
HighNote 2
BUSLOCKNote 3
POLL
BUFR/WNote 3
BUFENNote 3
X1
X2
CLKOUT
BS0 to BS2 Note 3
QS0, QS1
TOUT2
TCTL2
TCLK
INTP1 to INTP7
INTAK/SRDY/TOUT1
Input/Output
3-state I/O
3-state I/O
3-state output
3-state output
Output
Input
Output
Input
Output
Input
Input
3-state output
3-state output
3-state output
3-state output
Output
3-state output
3-state output
3-state output
Input
3-state output
3-state output
Input
—
Output
3-state output
Output
Output
Input
Input
Input
Output
Function
Time-division address/data bus
Time-division address/data bus
Address bus
Time-division address/processor status
Refresh request
Bus hold request
Bus hold acknowledge
Reset
System reset output
Bus cycle end
Non-maskable interrupt
Memory read strobe
Memory read strobe
I/O read strobe
I/O write strobe
Address strobe
Data bus upper byte enable
High level output
Bus lock
Floating-point operation processor polling
Buffer read/write
Buffer enable
Crystal/external clock
Clock output
Bus status
Queue status
Timer 2 output
Timer 2 control
Timer clock
Maskable interrupts
Interrupt acknowledge/serial reception ready/timer 1 output
Notes 1. V50HL only
2. V40HL only
3. These pins are provided with a latch. Therefore, when they go into a high-impedance state, they hold
the status before the high-impedance state until driven by an external device. It is not necessary to pull
up or down the data bus. To invert the level of the pin that goes into a high-impedance state by an
external device, a drive current higher than the latch invert current (IILH, IILL) is necessary.
Data Sheet U13225EJ4V0DS00
15