ISL6410 查看數據表（PDF） - Renesas Electronics

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ISL6410

Single Synchronous Buck Regulators with Integrated FET

Renesas Electronics 

ISL6410, ISL6410A

Pin Description

VIN - Supply voltage for the IC. It is recommended to place a

1µF decoupling capacitor as close as possible to the IC.

GND - Small signal ground for the PWM controller stage. All

internal control circuits are referenced to this pin.

PG - The Power good is an open-drain output. A pull-up

resistor should be connected between PG and VIN. It is

asserted active high when the output voltage reaches 94.5%

of the nominal value.

FB - The Feedback pin is used to sense the output voltage,

and should be connected to VOUT for normal operation.

VSET - This pin is used to program the output voltages. Refer

to Table 1 below for details.

TABLE 1.

VSET

ISL6410

Vo

ISL6410A

Vo

High

1.8V

3.3V

Open (NC)

1.5V

1.8V

Low

1.2V

1.2V

SYNC - This pin is used for synchronization. The converter

switching frequency can be synchronized to an external CMOS

clock signal in the range of (500kHz to 1MHz).

EN - A logic high enables the converter, logic low forces the

device into shutdown mode reducing the supply current to less

than 10A at 25°C. This pin should be pulled up to VCC via a

10K resistor.

L - This pin is the drain junction of the internal power

MOSFETs and is to be connected to the external inductor.

PGND - Power ground. Connect all power grounds to this pin.

PVCC - This pin provides the Input supply for the internal

MOSFETs. It is recommended to place a 1µF decoupling

capacitor as close as possible to the IC.

CT - Timing capacitor connection to set the 25ms minimum

pulse width for the RESET signal.

RESET - The outputs of the reset supervisory circuit, which

monitors VIN. The IC asserts these RESET signals whenever

the supply voltage drops below a preset threshold and keeps it

asserted for at least 25ms after VCC (VIN) has risen above the

reset threshold. These outputs are push-pull. RESET is LOW

when re-setting the microprocessor. The PWM will continue to

operate until VIN drops below the UVLO threshold.

Functional Description

The ISL6410, ISL6410A is a synchronous buck regulator with

integrated N- and P-channel power MOSFET and provides

pre-set pin programmable outputs. Synchronous rectification

with internal MOSFETs is used to achieve higher efficiency and

reduced number of external components. Operating frequency

of 750kHz typical allows the use of small inductor and

capacitor values. The device can be synchronized to an

external clock signal in the range of 500kHz to 1MHz. The PG

output indicates loss of regulation on PWM output.

The PWM is based on the peak current mode control topology

with internal slope compensation. At the beginning of each

clock cycle, the high side P-channel MOSFET is turned on.

The current in the inductor ramps up and is sensed via an

internal circuit. On exceeding a preset limit the high side switch

is turned off causing the PWM comparator to trip. This occurs

whenever the output voltage is in regulation or when the

inductor current reaches the current limit. After a minimum

dead time to prevent shoot through current, the low side N-

channel MOSFET turns on and the current ramps down. As the

clock cycle is completed, the low side switch turns off and the

next clock cycle is initiated.

The control loop is internally compensated thus reducing the

amount of external components.

The switch current is internally sensed and the maximum

current limit is 1300mA peak.

Synchronization

The typical operating frequency for the converter is 750kHz. It

is possible to synchronize the converter to an external clock

frequency in the range of 500kHz to 1000kHz when an external

signal is applied to SYNC pin. The device will automatically

detect and synchronize to the rising edge of the first clock

pulse. If the clock signal is stopped, the converter

automatically switches back to the internal clock and continues

its operation without interruption. The switch over will be

initiated if no rising edge triggers are present on the SYNC pin

for a duration of four clock cycles.

Soft-Start

As the EN (Enable) pin goes high, the soft-start function will

generate an internal voltage ramp. This causes the start-up

current to slowly rise preventing output voltage overshoot and

high inrush currents. The soft-start duration is typically 5.5ms

with 750kHz switching frequency. When the soft-start is

completed, the error amplifier will be connected directly to the

internal voltage reference.

Enable

Logic low on EN pin forces the PWM section into shutdown. In

the shutdown mode all the major blocks of the PWM including

power switches, drivers, voltage reference, and oscillator are

turned off.

Undervoltage Lockout

An undervoltage lockout circuit prevents the converter from

turning on when the voltage on VIN is less than the values

specified in the Input UVLO Threshold section of the electrical

specification.

FN9149 Rev 3.00

September 17, 2004

Page 7 of 13

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