HD74LV595A
8-bit Shift Registers with 3-state Outputs
ADE-205-281 (Z)
1st Edition
April 1999
Description
This device each contains an 8-bit serial-in, parallel-out shift registers that feeds an 8-bit D-type storage
register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift
register anf the storage register. The shift register has a direct-overriding clear, serial input, and serial
output pins for cascading.
Both the shift register anf the storage register clocks are positive-edge triggered. If the user wishes to
connect both clocks together, the shift register state will always be one clock pulse ahead of the storage
register. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook
computers), and the low-power consumption extends the battery life.
Features
• VCC = 2.0 V to 5.5 V operation
• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
• All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)
• Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)