HD74ACT161FPEL 查看數據表（PDF） - Renesas Electronics
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HD74ACT161FPEL Datasheet PDF : 9 Pages
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HD74ACT161/HD74ACT163
Capacitance
Item
Input capacitance
Power dissipation capacitance
Symbol
CIN
CPD
Typ
4.5
45.0
Unit
pF
pF
VCC = 5.5 V
VCC = 5.0 V
Condition
AC Characteristics: HD74ACT163
Ta = +25°C
Ta = –40°C to +85°C
Item
Maximum count
frequency
Symbol VCC (V)*1
fmax
5.0
CL = 50 pF
Min Typ Max
120 128 —
CL = 50 pF
Min
Max
105
—
MHz
Unit
Propagation delay
tPLH
5.0
CP to Qn (PE Input
HIGH or LOW)
1.0 5.5 10.0 1.0
11.0
ns
Propagation delay
tPHL
5.0
CP to Qn (PE Input
HIGH or LOW)
1.0 6.0 11.0 1.0
12.0
ns
Propagation delay
tPLH
5.0
CP to TC
1.0 7.0 11.5 1.0
13.5
ns
Propagation delay
tPHL
5.0
CP to TC
1.0 8.0 13.5 1.0
15.0
ns
Propagation delay
tPLH
5.0
CET to TC
1.0 5.5 9.0 1.0
10.5
ns
Propagation delay
tPHL
5.0
CET to TC
1.0 6.0 10.0 1.0
11.0
ns
Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V
AC Operating Requirements: HD74ACT163
Ta = –40°C
Ta = +25°C
to +85°C
Item
Set-up time, HIGH or LOW
Pn to CP
Hold time, HIGH or LOW
Pn to CP
Setup time, HIGH or LOW
SR to CP
CL = 50 pF
CL = 50 pF
Symbol VCC (V)*1
Typ
Guaranteed Minimum
tsu
5.0
4.0
10.0
12.0
ns
th
5.0
–5.0
0.5
0.5
ns
tsu
5.0
4.0
10.0
11.5
ns
Unit
Hold time, HIGH or LOW
th
5.0
–5.5
–0.5
–0.5
ns
SR to CP
Setup time, HIGH or LOW
tsu
5.0
4.0
8.5
10.5
ns
PE to CP
Hold time, HIGH or LOW
th
5.0
–5.5
–0.5
0
ns
PE to CP
Setup time, HIGH or LOW
tsu
5.0
2.5
5.5
6.5
ns
CEP or CET to CP
Hold time, HIGH or LOW
th
5.0
–3.0
0
CEP or CET to CP
0.5
ns
Clock pulse width (Load)
tw
5.0
2.0
3.5
3.5
ns
HIGH or LOW
Clock pulse width (Count)
tw
5.0
2.0
3.5
3.5
ns
HIGH or LOW
Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V
Rev.2.00, Jul.16.2004, page 6 of 8
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