CY2305ZC-1 查看數據表（PDF） - Cypress Semiconductor

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CY2305ZC-1

Low Cost 3.3-V Zero Delay Buffer

Cypress Semiconductor 

CY2305, CY2309

Table 2. Pin Description for CY2309

Pin

Signal

13

VDD

14

CLKA3[4]

15

CLKA4[4]

16

CLKOUT[4]

Description

3.3-V supply

Buffered clock output, Bank A

Buffered clock output, Bank A

Buffered output, internal feedback on this pin

Select Input Decoding for CY2309

S2 S1 CLOCK A1–A4 CLOCK B1–B4

0

0

Three-state

Three-state

0

1

Driven

Three-state

1

0

Driven

Driven

1

1

Driven

Driven

CLKOUT[5]

Driven

Driven

Driven

Driven

Output Source

PLL

PLL

Reference

PLL

PLL Shutdown

N

N

Y

N

Figure 3. REF. Input to CLKA/CLKB Delay vs. Loading Difference between CLKOUT and CLKA/CLKB Pins

Zero Delay and Skew Control

All outputs must be uniformly loaded to achieve zero delay between the input and output. Because the CLKOUT pin is the internal

feedback to the PLL, its relative loading can adjust the input-output delay. This is shown in the above graph.

For applications requiring zero input-output delay, all outputs, including CLKOUT, must be equally loaded. Even if CLKOUT is not

used, it must have a capacitive load, equal to that on other outputs, for obtaining zero input-output delay. If input to output delay

adjustments are required, use Figure 3 to calculate loading differences between the CLKOUT pin and other outputs.

For zero output-output skew, be sure to load all outputs equally. For further information, refer to the application note titled “CY2305

and CY2309 as PCI and SDRAM Buffers.”

Notes

4. Weak pull down on all outputs

5. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.

Document Number : 38-07140 Rev. *M

Page 4 of 19

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