UPC1933GR 查看數據表（PDF） - NEC => Renesas Technology

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UPC1933GR

DC-DC CONVERTER CONTROL IC

NEC => Renesas Technology 

µ PC1933

2. CONFIGURATION AND OPERATION OF EACH BLOCK

Figure 2-1 Block Diagram

FB 8

II 1

Error amplifier

0.3 V

VREF 4

VCC 3

Reference

voltage

section

Dead time setting: 85 %

(internally fixed)

DLY

2

CDLY

Soft start

select switch

Oscillation

section

PWM

comparator

Under voltage

lock-out

section

Output

section

SCP

comparator

Q1

Q2

1.92 V

SQ

Q

Timer latch for

short-circuit

protection section

7 RT

5 OUT

6 GND

2.1 Reference Voltage Generator

The reference voltage generator is comprised of a band-gap reference circuit, and outputs a temperature-compensated

reference voltage (2.1 V). The reference voltage can be used as the power supply for internal circuits, or as a reference

voltage, and can also be accessed externally via the VREF pin (pin 4).

2.2 Oscillator

The oscillator self-oscillates if a timing resistor is attached to the RT pin (pin 7). This oscillator waveform is input to the

inverted input pin of the PWM comparator to determine the oscillation frequency.

2.3 Under Voltage Lock-out Circuit

The under voltage lock-out circuit prevents malfunctioning of the internal circuits when the supply voltage is low, such as

when the supply voltage is first applied, or when the power supply is interrupted. When the voltage is low, the output

transistor is cut off at the same time.

2.4 Error Amplifier

The non-inverted input pin of the error amplifier is connected internally to 0.3 V (the input threshold voltage is 0.3 V

(TYP.)). The first stage of the error amplifier is a P-channel MOS transistor input.

Data Sheet G13690EJ3V0DS00

11

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