CXD1217M 查看數據表（PDF） - Sony Semiconductor
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CXD1217M Datasheet PDF : 12 Pages
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CXD1217M
Description of Operation (See Block Diagram.)
The CXD1217 is applicable to four systems; namely, NTSC, PAL, PALM and SECAM. In order to realize them,
the following relative equations of Sub-carrier (4fsclN) and Clock (CLIN) are adopted .
NTSC
PAL
PALM
SECAM
Sub carrier
4fsc = 910fH
4fsc = 1135fH + 2fv
4fsc = 909fH
—
Clock
910fH
908fH
910fH
908fH
As it is obvious from the above equations, the 4fsc and clock frequency do not coincide with each other in the
PAL and PALM. Therefore matching of the clock frequency is carried out by providing PLL.
1 . MODE specified input
The CXD1217 provides four inputs to specify the respective modes.
∗ EXT input: Set this pin to VDD side, and it becomes into external synchronizing mode. At this time, the
counters in connection with the PLL Ioop as shown in the upper part of the block diagram
become into stand still state.
∗ MODE1 and MODE2 inputs: These are inputs for the system selection.
MODE1
MODE2
System
0
0
NTSC
0
1
SECAM
1
0
PALM
"0" → VSS
1
1
PAL
"1" → VDD
∗ TEST input: An input to be used to measure IC. This input is normally kept opened.
(Because it is dropped internally to Vss with MOS resistance.)
2. Reset operation
The CXD1217 has three reset inputs ; namely, HRI, VRI, LALTRI, and it works to perform reset operation
when it detects falling edge. These three inputs are so designed as to take in synchronization with the IC
internal clock. Therefore, it is a prerequisite that both systems should have clock frequencies that are matched
as a reset operation to each other (GEN Iocked).
• H reset (HRI input)
When the HRI input is continuous with H synchronization, resetting is activated with the initial falling edge,
and for the subsequent edges they do not have to be reset unless they are deviated more than 2-bit (140ns)
against the initial edge in the internal clock. That is, if the jitter of HRI input is less than 140ns, it is absorbed.
The minimum resetting pulse width is over 0.3µs.
The phase to be reset is the advanced point of 6.3 to 6.37µs (= 90 to 91-bit × 70ns) than the HRI input as
shown in the diagram below.
HRI input
CXD1217
HD OUT output
Reset
–5–
6.3 to 6.37 [µs]
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