EBS52UC8APFA 查看數據表（PDF） - Elpida Memory, Inc
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EBS52UC8APFA Datasheet PDF : 14 Pages
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EBS52UC8APFA
Test Conditions
• Input and output timing reference levels: 1.4V
• Input waveform and output load: See following figures
2.4V
2.0V
0.4V 0.8V
DQ
CL
tT
tT
Input Waveform and Output Load
Relationship Between Frequency and Minimum Latency (SDRAM device specification)
Parameter
-7A
-75
Frequency (MHz)
133
133
133
tCK (ns)
7.5
7.5
7.5
/CAS latency
Symbol
CL = 3
CL = 2
CL = 3
Active command to column command
(same bank)
lRCD
2
2
3
Active command to active command
(same bank)
lRC
8
8
9
Active command to precharge command
(same bank)
lRAS
6
6
6
Precharge command to active command
(same bank)
lRP
2
2
3
Write recovery or data-in to precharge
command (same bank)
lDPL
2
2
2
Active command to active command
(different bank)
lRRD
2
2
2
Self refresh exit time
lSREX
1
1
1
Last data in to active command
(Auto precharge, same bank)
lDAL
4
4
5
Self refresh exit to command input
lSEC
8
8
9
Precharge command to high impedance lHZP
3
2
3
Last data out to active command
(Auto precharge, same bank)
lAPR
1
1
1
Last data out to precharge (early
precharge)
lEP
–2
–1
–2
Column command to column command lCCD
1
1
1
Write command to data in latency
lWCD
0
0
0
DQM to data in
lDID
0
0
0
DQM to data out
lDOD
2
2
2
CKE to CLK disable
lCLE
1
1
1
Register set to active command
lMRD
2
2
2
/CS to command disable
lCDD
0
0
0
Power down exit to command input
lPEC
1
1
1
Notes: 1. IRCD to IRRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]
Notes
1
1
1
1
1
1
2
= [lDPL + lRP]
= [lRC]
3
Data Sheet E0208E20 (Ver. 2.0)
10
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