HSP50415 查看數據表（PDF） - Renesas Electronics
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HSP50415 Datasheet PDF : 29 Pages
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HSP50415
resulting 23-bit output rounded at bit position 5 (multOut<5>)
to 17-bits. The extra bit is carried to check for overflow at the
output of the shifter. The output of the multiplier
(multOut<22:6>) is then shifted to the appropriate position
per the exponent bits with a shift value of 0xB positioning the
data at the top of the shifter. The final shifted output is then
checked for saturation and limited to 16-bits before being
output.
Fixed Coefficient 19-TAP Interpolating
Halfband
Following the post-FIR gain stage is a pair of fixed coefficient
19-tap interpolate by 2 halfband filters. The halfband filter
may be totally bypassed if not required. If bypassed, the data
to the filter is zeroed which reduces power consumption. The
halfband filter coefficients are:
1, 0, -17, 0, 87, 0, -299, 0, 1252, 2048, 1252, 0, -299, 0, 87,
0, -17, 0, 1
The interpolate by 2 is accomplished via zero-stuffing and
low-pass filtering. The output of this filter is rounded to 16-
bits. The output is checked for saturation and limited if
necessary. The data exits the halfband filters as a parallel
I<15:0> and Q<15:0> data stream at the interpolated sample
rate. Figure 8 shows the frequency response of the Half-Band
filter.
100
80
60
40
20
0
-20
-40
-60
-80
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
NORMALIZED FREQUENCY (NYQUIST = 1)
FIGURE 8. HALF-BAND FREQUENCY RESPONSE
Interpolating Filter
Following the halfband stage, the data enters the last stage
of interpolating filters. Again, the I and Q filters are identical
so the subsequent discussion will refer to a single channel.
The data is input to the interpolating filter at this stage’s input
sample rate which is dependent on the previous stage’s
interpolation rate. At this stage the input sample rate clock is
generated by the SYMBOL NCO. For every output sample
generated, there is a 12-bit phase value that is also
generated in the SYMBOL NCO (the top 12-bits of the phase
accumulator). The Interpolator uses this phase value to
compute output samples at the output sample rate (FSOUT)
which is the final output sample rate of the chip. The nulls in
the interpolation filter frequency response align with the
interpolation images of the shaping filter. Input to this stage
should be no greater than -2dB fullscale to prevent overflow.
The impulse response of the Interpolation filter is shown in
Figures 9 through 11 for an interpolate by 16 filter (the
interpolation ratio, L, is equal to 16). This block may be
bypassed if desired. Figures 12 through 17 depict the
response for varying interpolation ratios.
FN4559 Rev 6.00
Apr 23, 2007
Page 11 of 29
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