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HSP50415VI 查看數據表(PDF) - Renesas Electronics

零件编号
产品描述 (功能)
比赛名单
HSP50415VI
Renesas
Renesas Electronics Renesas
HSP50415VI Datasheet PDF : 29 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
HSP50415
NCO divider<13:0>
REFCLK divider<7:0>
REFCLK
8-BIT
COUNTER
14-BIT
COUNTER
carryOut
SYMBOL NCO
TC
14-bit countValue 8 upper bits of phaseAccum
CLK
SYNC enable
R
R
frequencyGain
freqError<15:0>
lagGain
phaseError<21:0>
FIGURE 2. PHASE/FREQUENCY ERROR DETECTOR
UL<31:0>
LL<13:0>
41
/
LIMITER
R
R
FIFOFreqError<8*7,7:0>
freqError<15:0>
_
phaseError<21:0>
DPLL
PhincError<31:0>
leadGain
FIGURE 3. DPLL LOOP FILTER
positive lockedValue
negative notLockedValue
threshold<20:0>
phaseErrorMag<20:0>
analogPLLlockStatus
useAPLLlockStatus
lockIntegrator<8>
LOCKDET
_
carryOut
AO
Z
A1
S
AO
A1 Z
S
R
lockIntegrator<8:0>
bit=1 indicates phaseErr > thld so NOT
locked
FIGURE 4. LOCK DETECTION BLOCK DIAGRAM
The Lock Detector compares the magnitude of the
phaseError to a programmable 21-bit threshold value. If the
carry out from this comparison is “1” then the phaseError is
greater than or equal to the threshold value and a negative
value is added to the lock integrator. If the carry out is “0”
then the phaseError is less than the threshold and a positive
value is added. As the phaseError magnitude stays below
the threshold level the lock integrator will grow from a
negative number to a positive one thus indicating a locked
condition. The lock integrator resets to a full-scale negative
value. The sign bit of the lock integrator is output as the
LOCKDET status flag. The values added or subtracted to the
lock integrator are user selectable as follows in Table 2.
TABLE 2. LOCK INTEGRATOR ADDENDS
LOCK FACTOR CARRY OUT ADDEND BINARY VALUE
0xx
1
-0.5
111111000
1xx
1
-0.25
111111100
x00
0
+0.0625
000000001
x01
0
+0.1250
000000010
x10
0
+0.2500
000000100
x11
0
+0.5000
000001000
FN4559 Rev 6.00
Apr 23, 2007
Page 8 of 29

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