GS1582 查看數據表（PDF） - Semtech Corporation
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GS1582
Semtech Corporation
GS1582 Datasheet PDF : 115 Pages
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Table 1-1: Pin Descriptions (Continued)
Pin
Number
H3
H4
H5
H6
H7
H8
Name
Timing
Type Description
ANC_BLANK
LOCKED
GRP2_EN/DIS
GRP1_EN/DIS
AUDIO_INT
JTAG/HOST
Non
Synchronous
Synchronous
with PCLK
Non
Synchronous
Non
Synchronous
Non
Synchronous
Non
Synchronous
Input
Output
Input
Input
Output
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable ANC data blanking.
When set LOW, the HANC and VANC data is mapped to the
appropriate blanking levels.
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS / LVTTL compatible.
This signal is set HIGH by the device when the internal PLL has
achieved lock to the supplied PCLK signal.
This pin is set LOW by the device under all other conditions.
IO_VDD = 3.3V
Drive Strength = 8mA
IO_VDD = 1.8V
Drive Strength = 4mA
Enable Input for Audio Group 2.
Enable Input for Audio Group 1.
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Summary Interrupt from Audio Processing.
This signal is set HIGH by the device to indicate a problem with the
audio processing which requires the Host processor to interrogate
the interrupt status registers.
IO_VDD = 3.3V
Drive Strength = 8mA
IO_VDD = 1.8V
Drive Strength = 4mA
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select JTAG Test Mode or Host Interface Mode.
When set HIGH, CS_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are
configured for JTAG boundary scan testing.
When set LOW, CS_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are
configured as Gennum Serial Peripheral Interface (GSPI) pins for
normal host interface operation.
GS1582 Multi-Rate Serializer with Cable Driver, Audio
Multiplexer and ClockCleanerTM
Data Sheet
40117 - 4
December 2011
16 of 115
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