GS1582 查看數據表（PDF） - Semtech Corporation

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GS1582

Multi-Rate Serializer with Cable Driver, Audio Multiplexer and ClockCleaner™

Semtech Corporation 

List of Figures

Figure 3-1: Differential Output Stage (SDO/SDO) .............................................................................. 23

Figure 3-2: Charge Pump Current Setting Resistor (CP_RES) .......................................................... 23

Figure 3-3: PLL Loop Filter .......................................................................................................................... 24

Figure 3-4: VCO Input .................................................................................................................................. 24

Figure 3-5: Digital Input Pin with Weak Pull Up(>33kW) ................................................................ 25

Figure 3-6: 5V Tolerant Input Pin (All Other Input Pins) .................................................................. 25

Figure 3-7: Digital Output Pin with High Impedance Mode ............................................................ 25

Figure 4-1: PCLK to Data Timing ............................................................................................................... 27

Figure 4-2: H_Blanking, V_Blanking, F_Digital Timing .................................................................... 30

Figure 4-3: HSYNC:VSYNC:DE Input Timing 1280 x 720p @ 59.94/60 ....................................... 32

Figure 4-4: HSYNC:VSYNC:DE Input Timing 1920 x 1080i @ 59.94/60 ...................................... 32

Figure 4-5: HSYNC:VSYNC:DE Input Timing 720 (1440) x 480i @ 59.94/60 ............................. 33

Figure 4-6: HSYNC:VSYNC:DE Input Timing 1280 x 720p @ 50 ................................................... 34

Figure 4-7: HSYNC:VSYNC:DE Input Timing 1920 x 1080i @ 50 .................................................. 34

Figure 4-8: HSYNC:VSYNC:DE Input Timing 720 (1440) x 576 @ 50 ........................................... 35

Figure 4-9: DVB-ASI FIFO Implementation using the GS1582 ....................................................... 36

Figure 4-10: Audio Multiplexer Top Level ............................................................................................ 38

Figure 4-11: Ancillary Data Packet Placement Example .................................................................. 40

Figure 4-12: SD Audio Data Packet Structure ...................................................................................... 42

Figure 4-13: SD Extended Audio Data Packet Structure .................................................................. 43

Figure 4-14: HD Audio Data Packet Structure ..................................................................................... 44

Figure 4-15: SD Audio Control Packet Structure ................................................................................. 46

Figure 4-16: HD Audio Control Packet Structure ................................................................................ 47

Figure 4-17: Audio Group Replacement Example (HD Formats) .................................................. 50

Figure 4-18: ACLK to Data & Control Signal Input Timing ............................................................... 52

Figure 4-19: AES/EBU Sub-frame Formatting ...................................................................................... 55

Figure 4-20: AES/EBU Audio Input Format .......................................................................................... 55

Figure 4-21: Serial Audio Input: Left Justified; MSB First ................................................................. 56

Figure 4-22: Serial Audio Input: Left Justified; LSB First .................................................................. 56

Figure 4-23: Serial Audio Input: Right Justified; MSB First .............................................................. 56

Figure 4-24: Serial Audio Input: Right Justified; LSB First ............................................................... 56

Figure 4-25: I2S Audio Input ...................................................................................................................... 56

Figure 4-26: Gennum Serial Peripheral Interface (GSPI) .................................................................. 78

Figure 4-27: Command Word .................................................................................................................... 79

Figure 4-28: Data Word ............................................................................................................................... 79

Figure 4-29: GSPI Read Mode Timing ..................................................................................................... 80

Figure 4-30: GSPI Write Mode Timing .................................................................................................... 80

Figure 4-31: In-Circuit JTAG .................................................................................................................... 107

Figure 4-32: System JTAG ......................................................................................................................... 107

Figure 4-33: Reset Pulse ............................................................................................................................. 108

Figure 7-1: Pb-free Solder Reflow Profile ............................................................................................ 114

GS1582 Multi-Rate Serializer with Cable Driver, Audio

Multiplexer and ClockCleanerTM

Data Sheet

40117 - 4

December 2011

6 of 115

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