IN74HC652 查看數據表（PDF） - Integral Corp.

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IN74HC652

OCTAL 3-STATE BUS TRANSCEIVERS AND D FLIP-FLOPS High-Performance Silicon-Gate CMOS

Integral Corp. 

IN74HC652

AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)

VCC

Guaranteed Limit

Symbol

Parameter

V 25 °C ≤85°C ≤125 Unit

to

°C

-55°C

tPLH, Maximum Propagation Delay, Input A to 2.0 180 225 270 ns

tPHL Output B (or Input B to Output A) 4.5 36

45

54

(Figures 2,3 and 9)

6.0 31

38

46

tPLH, Maximum Propagation Delay, A-to-B 2.0 240 300 360 ns

tPHL Clock to Output B (or B-to-A Clock to 4.5 48

60

72

Output

A) 6.0 41

51

61

(Figures 1 and 9)

tPLH, Maximum Propagation Delay, A-to-B 2.0 220 275 330 ns

tPHL Source to Output B (or B-to-A Source to 4.5 44

55

66

Output A) (Figures 4 and 9)

6.0 37

47

56

tPLZ, Maximum Propagation Delay , Direction 2.0 170 215 255 ns

tPHZ or Output Enable to Output A or B 4.5 34

43

51

(Figures 5,6 and 10)

6.0 29

37

43

tPZL, Maximum Propagation Delay , Direction 2.0 180 225 270 ns

tPZH or Output Enable to Output A or B 4.5 36

45

54

(Figures 5,6 and 10)

6.0 31

38

46

tTLH, tTHL Maximum Output Transition Time, Any 2.0 60

75

90 ns

Output

4.5 12

15

18

(Figure 2)

6.0 10

13

15

CIN Maximum Input Capacitance

- 10

10

10 pF

COUT Maximum Three-State I/O Capacitance -

15

15

15 pF

(Output in High-Impedance State

Power Dissipation Capacitance (Per Typical @25°C,VCC=5.0 V

Channel)

CPD Used to determine the no-load dynamic

60

pF

power

consumption:

PD=CPDVCC2f+ICCVCC

4

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