ML6694 查看數據表（PDF） - Micro Linear Corporation
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ML6694 Datasheet PDF : 12 Pages
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ML6694
AC ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
MII (Media-Independent Interface)
XBTOL
TX Output Clock Frequency
Tolerance
25MHz frequency
–100
+100
ppm
tTPWH
tTPWL
tRPWH
tRPWL
tTPS
TXC pulse width HIGH
TXC pulse width LOW
RXC pulse width HIGH
RXC pulse width LOW
Setup time, TSM<4:0> Data Valid
to TXC Rising Edge (1.4V point)
14
ns
14
ns
14
ns
14
ns
12
ns
tTPH
Hold Time, TSM<4:0> Data
Valid After TXC Rising Edge
(1.4V point)
3
ns
tRCS
Time that RSM<4:0> Data are
Valid Before RXC Rising Edge
(1.4V point)
10
ns
tRCH
Time that RSM<4:0> Data are
Valid After RXC Rising Edge
(1.4V point)
10
ns
tRPCR
RXC 10% – 90% Rise Time
6
ns
tRPCF
RXC 90%-10% Fall Time
6
ns
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
Note 7.
Note 8.
Note 9.
Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.
Measured using the test circuit shown in Fig. 1, under the following conditions:
RLP = 200Ω, RLS = 49.9Ω, RTSET = 2.49kΩ.
All resistors are 1% tolerance.
Output current amplitude is IOUT = 40 ϫ 1.25V/RTSET.
Measured relative to ideal negative and positive signal 50% points, using the four successive MLT-3 transitions for the 01010101 bit sequence.
Time difference between 10% and 90% levels of the transition from the baseline voltage (nominally zero) to either the positive or negative peak signal voltage. The
times specified here correlate to the transition times defined in the ANSI X3T9.5 TP-PMD Rev 2.0 working draft, section 9.1.6, which include the effects of the
external network coupling transformer and EMI/RFI emissions filter.
Differential test load is shown in fig. 1 (see note 3).
Defined as the percentage excursion of the differential signal transition beyond its final adjusted value during the symbol interval following the transition. The
adjusted value is obtained by doing a straight line best-fit to an output waveform containing 14 bit-times of no transition preceded by a transition from zero to
either a positive or negative signal peak; the adjusted value is the point at which the straight line fit meets the rising or falling signal edge.
Symbol /J/ at TSM <4:0> sampled by TXC to first bit of /J/ at MDI.
First bit of /J/ at MDI to first rising edge of RXC after the last part of the /J/ appears at RSM <4:0>.
VCC
TPOUTP
RLP
2:1
200Ω
1
TPOUTN
RLP
200Ω
RLS
49.9Ω
2
RLS
49.9Ω
Figure 1. Test Circuit
7
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