NOIL2SM1300A(2014) 查看數據表（PDF） - ON Semiconductor
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NOIL2SM1300A Datasheet PDF : 44 Pages
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NOIL2SM1300A
LVDS Block
The LVDS block is positioned below the data block. It
receives a differential clock signal, transmits differential
data over the 12 data channels, and transmits a LVDS clock
signal and a synchronization signal over the clock and
synchronization channel.
A number of LVDS transmitter blocks are placed in
parallel to serve all data, clock, and synchronization output
channels. A high level overview is illustrated in the
following figure.
Serializer
Se rialize r<0 >
… Serializer <1>
Serializer <11>
cloc kge nerato r Se rializer
LVDS
Transmitter
clock
LVDS
Transmitter
<0>
LVDS
Transmitter
<1>
LVDS
Transmitter
<11>
LVDS
Receiver
LVDS
Transmitter
Synch
Figure 9. LVDS Block − High Level Overview
The function of this block is to take 10 bits of the protocol
block, serialize these bits, and converts them to an LVDS
standard (TIA/EIA 644A) compatible differential output
signal. The block must also provide a clock to the host, to
allow data recovery. This clock is an on-chip version of the
clock coming from the host.
Sequencer and Logic
The sequencer generates the complete internal timing of
the pixel array and the readout. The timing can be controlled
by the user through the SPI register settings. The sequencer
operates on the same clock as the data block. This is a
division by 10 of the input clock (internally divided).
Table 9 lists the internal registers. These registers are
discussed in detail in Detailed Description of Internal
Registers on page 15.
Table 9. INTERNAL REGISTERS
Block Register Name Address [6..0]
MBS
Fix1
0
(reserved)
Fix2
1
Fix3
2
Fix4
3
Fix5
4
LVDS clk lvdsmain
5
divider
lvdspwd1
6
lvdspwd2
7
Fix6
8
AFE
afebias
9
afemode
10
afepwd1
11
Field
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[3:0]
[7:4]
[7:0]
[5:0]
[6]
[7]
[7:0]
[3:0]
[2:0]
[5:3]
[6]
[7:0]
Reset Value
Description
0x00
Reserved, fixed value
0xFF
Reserved, fixed value
0x00
Reserved, fixed value
0x00
Reserved, fixed value
0x08
Reserved, fixed value
‘0110’
lvds trim
0
clkadc phase
0x00
Power down channel 7:0
0
Power down channel 13:8
0
Power down all channels
0
lvds test mode
0x00
Reserved, fixed value
‘1000’
afe current biasing
‘111’
vrefp, vrefm settings
‘000’
Pga settings
0
Power down AFE
0x00
Power down adc_channel_2x 7 to 0
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