UT62257CSC-70LL(2001) 查看數據表（PDF） - Utron Technology Inc

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UT62257CSC-70LL
(Rev.:2001)

32K X 8 BIT LOW POWER CMOS SRAM

Utron Technology Inc 



Rev. 1.0

UTRON

UT62257C

32K X 8 BIT LOW POWER CMOS SRAM

DATA RETENTION CHARACTERISTICS (TA = 0℃ to 70℃)

PARAMETER

Vcc for Data Retention

Data Retention Current

Chip Disable to Data

Retention Time

Recovery Time

tRC* = Read Cycle Time

SYMBOL TEST CONDITION

MIN. TYP. MAX. UNIT

VDR

CE1 ≧ VCC-0.2V

2.0 - 5.5 V

or CE2 ≤ 0.2V

IDR

Vcc=3V, CE2 ≤ 0.2V - L - 1 50 µA

or CE1 ≧ VCC-0.2V - LL - 0.5 20 µA

tCDR See Data Retention

Waveforms (below)

0 - - ns

tR

tRC*

-

- ns

DATA RETENTION WAVEFORM

VCC

CE1

VSS

CE2

4.5V

tCDR

VIH

VIL

Date Retention Mode

VDR ≧ 2V

CE1 ≧ VCC -0.2V

CE2 ≤ 0.2V

4.5V

tR

VIH

VIL

UTRON TECHNOLOGY INC.

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882 FAX: 886-3-5777919

6

P80062

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